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uPSD3212A, uPSD3212C, uPSD3212CV
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0-
FS3, CSBOOT0-CSBOOT1), and SRAM Select
(RS0) equations.
The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0-
FS3, CSBOOT0-CSBOOT1), and SRAM Select
(RS0) equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure
shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
Figure 53. Page Register
RESET
D 0 - D 7
R / W
D 0
Q 0
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
D 1
D 2
D 3
D 4
D 5
D 6
D 7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
CPLD
INTERNAL PSD MODULE
SELECTS
AND LOGIC
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI05799
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