Инструкции для Texas TMS320C645X

Содержание

• Table of Contents

  3
• Preface

  13
• 1 Overview

  14
  • 1.1 General RapidIO System

    14
  • 1.2 RapidIO Feature Support in SRIO

    17
  • 1.3 Standards

    18
  • 1.4 External Devices Requirements

    18
• 2 SRIO Functional Description

  19
  • 2.1 Overview

    19
  • 2.2 SRIO Pins

    24
  • 2.3 Functional Operation

    24
• 3 Logical/Transport Error Handling and Logging

  73
• 4 Interrupt Conditions

  74
  • 4.1 CPU Interrupts

    74
  • 4.2 General Description

    74
  • 4.3 Interrupt Condition Control Registers

    75
  • 4.4 Interrupt Status Decode Registers

    83
  • 4.5 Interrupt Generation

    85
  • 4.6 Interrupt Pacing

    85
  • 4.7 Interrupt Handling

    86
• 5 SRIO Registers

  88
  • 5.1 Introduction

    88
  • 5.2 Peripheral Identification Register (PID)

    99
  • 5.3 Peripheral Control Register (PCR)

    100
  • 5.4 Peripheral Settings Control Register (PER_SET_CNTL)

    101
  • 5.5 Peripheral Global Enable Register (GBL_EN)

    104
  • 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)

    105
  • 5.7 Block n Enable Register (BLKn_EN)

    106
  • 5.8 Block n Enable Status Register (BLKn_EN_STAT)

    107
  • 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)

    108
  • 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)

    109
  • 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn)

    110
  • 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn)

    111
  • 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL)

    112
  • 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL)

    114
  • 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)

    116
  • 5.16 DOORBELLn Interrupt Status Register (DOORBELLn_ICSR)

    117
  • 5.17 DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR)

    118
  • 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)

    119
  • 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)

    120
  • 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)

    121
  • 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)

    122
  • 5.22 LSU Status Interrupt Register (LSU_ICSR)

    123
  • 5.23 LSU Clear Interrupt Register (LSU _ICCR)

    124
  • 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR)

    125
  • 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR)

    126
  • 5.26 DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR)

    127
  • 5.27 DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2)

    128
  • 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR)

    129
  • 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2)

    130
  • 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR)

    131
  • 5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2)

    132
  • 5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0)

    133
  • 5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1)

    134
  • 5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2)

    135
  • 5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3)

    136
  • 5.36 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR)

    137
  • 5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2)

    138
  • 5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3)

    139
  • 5.39 INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE)

    140
  • 5.40 INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL)

    141
  • 5.41 LSUn Control Register 0 (LSUn_REG0)

    142
  • 5.42 LSUn Control Register 1 (LSUn_REG1)

    143
  • 5.43 LSUn Control Register 2 (LSUn_REG2)

    144
  • 5.44 LSUn Control Register 3 (LSUn_REG3)

    145
  • 5.45 LSUn Control Register 4 (LSUn_REG4)

    146
  • 5.46 LSUn Control Register 5 (LSUn_REG5)

    147
  • 5.47 LSUn Control Register 6 (LSUn_REG6)

    148
  • 5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n)

    149
  • 5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP)

    150
  • 5.50 Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP)

    151
  • 5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP)

    152
  • 5.52 Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP)

    153
  • 5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)

    154
  • 5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn)

    155
  • 5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)

    157
  • 5.56 Receive CPPI Control Register (RX_CPPI_CNTL)

    158
  • 5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0)

    159
  • 5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1)

    160
  • 5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2)

    161
  • 5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3)

    162
  • 5.61 Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln)

    163
  • 5.62 Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn)

    164
  • 5.63 Flow Control Table Entry Registers (FLOW_CNTLn)

    165
  • 5.64 Device Identity CAR (DEV_ID)

    166
  • 5.65 Device Information CAR (DEV_INFO)

    167
  • 5.66 Assembly Identity CAR (ASBLY_ID)

    168
  • 5.67 Assembly Information CAR (ASBLY_INFO)

    169
  • 5.68 Processing Element Features CAR (PE_FEAT)

    170
  • 5.69 Source Operations CAR (SRC_OP)

    171
  • 5.70 Destination Operations CAR (DEST_OP)

    172
  • 5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL)

    173
  • 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)

    174
  • 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)

    175
  • 5.74 Base Device ID CSR (BASE_ID)

    176
  • 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)

    177
  • 5.76 Component Tag CSR (COMP_TAG)

    178
  • 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD)

    179
  • 5.78 Port Link Time-Out Control CSR (SP_LT_CTL)

    180
  • 5.79 Port Response Time-Out Control CSR (SP_RT_CTL)

    181
  • 5.80 Port General Control CSR (SP_GEN_CTL)

    182
  • 5.81 Port Link Maintenance Request CSR n (SPn_LM_REQ)

    183
  • 5.82 Port Link Maintenance Response CSR n (SPn_LM_RESP)

    184
  • 5.83 Port Local AckID Status CSR n (SPn_ACKID_STAT)

    185
  • 5.84 Port Error and Status CSR n (SPn_ERR_STAT)

    186
  • 5.85 Port Control CSR n (SPn_CTL)

    188
  • 5.86 Error Reporting Block Header (ERR_RPT_BH)

    190
  • 5.87 Logical/Transport Layer Error Detect CSR (ERR_DET)

    191
  • 5.88 Logical/Transport Layer Error Enable CSR (ERR_EN)

    192
  • 5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)

    193
  • 5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)

    194
  • 5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)

    195
  • 5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)

    196
  • 5.93 Port-Write Target Device ID CSR (PW_TGT_ID)

    197
  • 5.94 Port Error Detect CSR n (SPn_ERR_DET)

    198
  • 5.95 Port Error Rate Enable CSR n (SPn_RATE_EN)

    199
  • 5.96 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)

    200
  • 5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)

    201
  • 5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)

    202
  • 5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)

    203
  • 5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)

    204
  • 5.101 Port Error Rate CSR n (SPn_ERR_RATE)

    205
  • 5.102 Port Error Rate Threshold CSR n (SPn_ERR_THRESH)

    206
  • 5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER)

    207
  • 5.104 Port IP Mode CSR (SP_IP_MODE)

    208
  • 5.105 Serial Port IP Prescalar (IP_PRESCAL)

    210
  • 5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPTn)

    211
  • 5.107 Port Reset Option CSR n (SPn_RST_OPT)

    212
  • 5.108 Port Control Independent Register n (SPn_CTL_INDEP)

    213
  • 5.109 Port Silence Timer n (SPn_SILENCE_TIMER)

    215
  • 5.110 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS)

    216
  • 5.111 Port Control Symbol Transmit n (SPn_CS_TX)

    217