Renesas rl78 用户手册

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

 

Symbol

SVA0

Address:  F0234H     After reset:  00H     R/W

7

6

5

4

3

2

1

0

0

A0

A1

A2

A3

A4

A5

A6

 

 

Note  Bit 0 is fixed to 0. 

The SO latch is used to retain the SDAA0 pin’s output level. 

 

This circuit generates an interrupt request (INTIICA0) when the address received by this register matches the 

address value set to the slave address register 0 (SVA0) or when an extension code is received. 

 

This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify 

that 8-bit data was transmitted or received. 

 

This circuit controls the generation of interrupt request signals (INTIICA0). 

An I

2

C interrupt request is generated by the following two triggers. 

•  Falling edge of eighth or ninth clock of the serial clock (set by the WTIM0 bit) 

•  Interrupt request generated when a stop condition is detected (set by the SPIE0 bit) 

 

Remark  WTIM0 bit:   Bit 3 of IICA control register 00 (IICCTL00) 

 

SPIE0 bit:   Bit 4 of IICA control register 00 (IICCTL00) 

 

In master mode, this circuit generates the clock output via the SCLA0 pin from a sampling clock. 

 

This circuit controls the wait timing. 

 

These circuits generate and detect each status. 

 

This circuit generates the hold time for data corresponding to the falling edge of the serial clock. 

 

This circuit generates a start condition when the STT0 bit is set to 1.  

However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY 

bit = 1), start condition requests are ignored and the STCF bit is set to 1.   

 

This circuit generates a stop condition when the SPT0 bit is set to 1.  

 

R01UH0305EJ0200  Rev.2.00 

 

 

570  

Jul 04, 2013