Renesas rl78 用户手册

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.   

However, as the bus status cannot be detected immediately following operation, the initial status is set by the 

STCEN bit.  

 

Remark  STT0 bit: 

Bit 1 of IICA control register 00 (IICCTL00) 

SPT0 bit: 

Bit 0 of IICA control register 00 (IICCTL00) 

 

IICRSV bit:  Bit 0 of IICA flag register 0 (IICF0) 

 

IICBSY bit:  Bit 6 of IICA flag register 0 (IICF0) 

 

STCF bit: 

Bit 7 of IICA flag register 0 (IICF0) 

 

STCEN bit:  Bit 1 of IICA flag register 0 (IICF0) 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013