Motorola DSP96002 用户手册

 

The upper 128 locations of the X and Y Data memories are defined as the I/O space. The Y memory I/O

space is wholly external, while the X memory I/O space is internal. The X memory I/O space is used to ad-

dress the I/O Interface registers as well as the bus, port select and interrupt control registers. Both I/O spac-

es may be accessed by regular X and Y memory MOVE instructions. The MOVEP instructions offer I/O

short addressing and memory to memory move capability for easy data transfers with the I/O mapped reg-

isters.

The on-chip I/O peripherals are intended to minimize system chip count and "glue" logic in many applica-

tions. Each I/O interface has its own control, status and data registers memory-mapped into the X memory

I/O space. Each interface has several dedicated interrupt vector addresses and control bits to enable/dis-

able interrupts. This minimizes the overhead associated with servicing the device since each interrupt

source has its own service routine.

Three on-chip peripherals are provided in the DSP96002: 

• 

a 32-bit parallel Host MPU/DMA Interface connected to Port A. 

• 

a 32-bit parallel Host MPU/DMA Interface connected to Port B. 

• 

a two-channel DMA Controller. 

 

The DSP96002 has two external expansion ports (Port A and Port B). Each port has a bus control register

where memory wait states may be specified, parameter and control bits for a page circuit dedicated to

DRAM/VRAM  memory support are located, and control bits for direct software control of 

—

B

–

R and 

—

B

–

L pins are found. 

 

There are 2 identical BCR registers, one for each port. The Bus Control Registers (BCRx) may be pro-

grammed to insert wait states in a bus cycle during external memory accesses. They are also used to pro-

gram the Page Fault circuitry and for direct software control of the 

—

B

–

R and 

—

B

–

L pins.