Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
92
Altera Corporation
32-Bit Instruction Set
ST16s
Store 16-Bit Data To Memory (Static Half-Word-Offset Address)
Operation:
Not preceded by PFX:
hn
Mem32[align32(RA)]
←
hn
R0 where n = IMM1
Preceded by PFX:
hn
Mem32[align32(RA + (
σ(K) × 4))] ←
hn
R0 where n = IMM1
Assembler Syntax:
ST16s [%rA],%r0,IMM1
Example:
ST16s [%g8],%r0,1
Description:
Not preceded by PFX:
Stores one of the two half-words of %r0 to memory at the half-word-aligned
Stores one of the two half-words of %r0 to memory at the half-word-aligned
address given by (RA[31..2] + IMM1
× 2). The two bits RA[1..0] are ignored.
IMM2 selects which half-word of %r0 is stored (half-word #1 is most significant).
ST16s may be used in combination with FILL16 to implement a half-word-store
operation to a half-word-offset from a word-aligned base-address. Given a half-
word held in bits 15..0 of any register %rX, the following sequence writes this half-
word held in bits 15..0 of any register %rX, the following sequence writes this half-
word to memory at the half-word-aligned address given by (RA + Y
× 2) (RA
presumed to hold a word-aligned pointer):
FILL16 %r0,%rX
PFX Y >> 2
ST16s [%rA],%r0,(Y >> 1) & 1
Preceded by PFX:
A 12-bit signed, half-word-scaled offset is formed by concatenating K with
A 12-bit signed, half-word-scaled offset is formed by concatenating K with
IMM1.This offset (K : IMM1) is half-word-scaled (multiplied by 2), sign-extended
to 32 bits, and used as the half-word-offset for the ST-operation.
to 32 bits, and used as the half-word-offset for the ST-operation.
Condition Codes:
Flags: Unaffected
Instruction Format:
Ri1u
Instruction Fields
A = Register index of operand RA
IMM1 = 1-bit immediate value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
0
1
1
0
1
IMM1
0
A
N
V
Z
C
−
−
−
−