Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
7
Getting
Overview
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CLR_IE(%ctl8)
Any WRCTL operation to the CLR_IE register clears the IE bit in the
STATUS register (IE
STATUS register (IE
← 0) and the WRCTL value is ignored. A RDCTL
operation from CLR_IE produces an undefined result.
SET_IE (%ctl9)
Any WRCTL operation to the SET_IE register sets the IE bit in the STATUS
register (IE
register (IE
← 1) and the WRCTL value is ignored. A RDCTL operation
from SET_IE produces an undefined result.
Memory Access
Overview
Overview
The Nios processor is little-endian. Data memory must occupy contiguous
native-words. If the physical memory device is narrower than the native-
word size, then the data bus should implement dynamic-bus sizing to
simulate full-width data to the Nios CPU. Peripherals present their
registers as native-word widths, padded by 0s in the most significant bits
if the registers happen to be smaller than native-words. Table 8 and
Table 9 show examples of the 32-bit Nios CPU native-word widths.
native-words. If the physical memory device is narrower than the native-
word size, then the data bus should implement dynamic-bus sizing to
simulate full-width data to the Nios CPU. Peripherals present their
registers as native-word widths, padded by 0s in the most significant bits
if the registers happen to be smaller than native-words. Table 8 and
Table 9 show examples of the 32-bit Nios CPU native-word widths.
Table 8. Typical 32-bit Nios CPU Program/Data Memory at Address 0x0100
Address
Contents
31 24 23 16 15 8 7 0
0x0100
byte 3
byte 2
byte 1
byte 0
0x0104
byte 7
byte 6
byte 5
byte 4
0x0108
byte 11
byte 10
byte 9
byte 8
0x010c
byte 15
byte 14
byte 13
byte 12
Table 9. N-bit-wide Peripheral at Address 0x0100 (32-bit Nios CPU)
Address
Contents
31 N N-1 0
0x0100
(zero padding)
register 0
0x0104
(zero padding)
register 1
0x0108
(zero padding)
register 2
0x010c
(zero padding)
register 3