Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
8
Altera Corporation
Overview
Reading from Memory (or Peripherals)
The Nios CPU can only perform aligned memory accesses. A 32-bit read
operation can only read a full word starting at a byte address that is a
multiple of 4. A 16-bit read operation can only read a half-word starting at
a byte address that is a multiple of 2. Instructions which read from
memory always treat the low bit (16-bit Nios CPU) or low two bits (32-bit
Nios CPU) of the address as 0. Instructions are provided for extracting
particular bytes and half-words from words.
operation can only read a full word starting at a byte address that is a
multiple of 4. A 16-bit read operation can only read a half-word starting at
a byte address that is a multiple of 2. Instructions which read from
memory always treat the low bit (16-bit Nios CPU) or low two bits (32-bit
Nios CPU) of the address as 0. Instructions are provided for extracting
particular bytes and half-words from words.
The simplest instruction that reads data from memory is the LD
instruction. A typical example of this instruction is
instruction. A typical example of this instruction is
LD %g3, [%o4]
. The
first register operand, %g3, is the destination register, where data will be
loaded. The second register operand specifies a register containing an
address to read from. This address will be aligned to the nearest half-word
(16-bit Nios CPU) or word (32-bit Nios CPU) meaning the lowest bit (16-
bit Nios CPU) or two bits (32-bit Nios CPU) will be treated as if they are 0.
loaded. The second register operand specifies a register containing an
address to read from. This address will be aligned to the nearest half-word
(16-bit Nios CPU) or word (32-bit Nios CPU) meaning the lowest bit (16-
bit Nios CPU) or two bits (32-bit Nios CPU) will be treated as if they are 0.
Quite often, however, software must read data smaller than the native
data size. The Nios CPU provides instructions for extracting individual
bytes (16-bit and 32-bit Nios CPU) and half-words (32-bit Nios CPU) from
native-words. The EXT8d instruction is used for extracting a byte, and the
EXT16d instruction is used for extracting a word. A typical example of the
EXT8d instruction is EXT8d %g3,%o4. The EXT8d instruction uses the
lowest bit (on 16-bit Nios CPU) or two bits (on 32-bit Nios CPU) of the
second register operand to extract a byte from the first register operand,
and replace the entire contents of the first register operand with that byte.
data size. The Nios CPU provides instructions for extracting individual
bytes (16-bit and 32-bit Nios CPU) and half-words (32-bit Nios CPU) from
native-words. The EXT8d instruction is used for extracting a byte, and the
EXT16d instruction is used for extracting a word. A typical example of the
EXT8d instruction is EXT8d %g3,%o4. The EXT8d instruction uses the
lowest bit (on 16-bit Nios CPU) or two bits (on 32-bit Nios CPU) of the
second register operand to extract a byte from the first register operand,
and replace the entire contents of the first register operand with that byte.
The assembly-language example in Code Example 1 shows how to read a
single byte from memory, even if the address of the byte is not native-
word-aligned.
single byte from memory, even if the address of the byte is not native-
word-aligned.
Code Example 1: Reading a Single Byte from Memory
Contents of memory:
; 0 1 2 3
; 0x00001200 0x46 0x49 0x53 0x48
; 0x00001200 0x46 0x49 0x53 0x48
;Instructions executed on a 32-bit Nios CPU
; Let’s assume %o4 contains the address
x00001202
LD %g3,[%o4]
LD %g3,[%o4]
; %g3 gets the contents of address 0x1200,
; so %g3 contains 0x48534946
; so %g3 contains 0x48534946
EXT8d %g3,%o4
; %g3 gets replaced with byte 2 from %g3,
; so %g3 contains 0x00000053
; so %g3 contains 0x00000053