Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
42
Altera Corporation
32-Bit Instruction Set
BR
Branch
Operation:
PC
← PC + ((σ(IMM11) + 1) << 1)
Assembler Syntax:
BR addr
Example:
BR MainLoop
NOP ; (delay slot)
Description:
The offset given by IMM11 is interpreted as a signed number of half-words
(instructions) relative to the instruction immediately following BR. Program control
(instructions) relative to the instruction immediately following BR. Program control
is transferred to instruction at this offset.
Condition Codes:
Flags: Unaffected
Delay Slot Behavior:
The instruction immediately following BR (BR’s delay slot) is executed after BR,
but before the destination instruction. There are restrictions on which instructions
may be used as a delay slot. (Refer to “Branch Delay Slots” on page 23)
may be used as a delay slot. (Refer to “Branch Delay Slots” on page 23)
Instruction Format:
i11
Instruction Fields:
IMM11 = 11-bit immediate value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
IMM11
N
V
Z
C
−
−
−
−