Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
43
32323232
32-Bit Instruction Set
2
3
2
-B
it In
st
st
ru
ctio
n
n
Se
t
t
BSR
Branch To Subroutine
Operation:
%o7
← ((PC + 4) >> 1)
PC
← PC + ((σ(IMM11) + 1) << 1)
Assembler Syntax:
BSR addr
Example:
BSR SendCharacter
NOP ; (delay slot)
Description:
The offset given by IMM11 is interpreted as a signed number of half-words
(instructions) relative to the instruction immediately following BR. Program control
is transferred to instruction at this offset. The return-address is the address of the
is transferred to instruction at this offset. The return-address is the address of the
BSR instruction plus four, which is the address of the second subsequent
instruction. The return-address is shifted right one bit and stored in %o7. The
instruction. The return-address is shifted right one bit and stored in %o7. The
right-shifted value stored in %o7 is a destination suitable for direct use by JMP
without modification.
without modification.
Condition Codes:
Flags: Unaffected
Delay Slot Behavior:
The instruction immediately following BSR (BSR’s delay slot) is executed after
BSR, but before the destination instruction. There are restrictions on which
BSR, but before the destination instruction. There are restrictions on which
instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on
page 23)
page 23)
Instruction Format:
i11
Instruction Fields:
IMM11 = 11-bit immediate value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
1
IMM11
N
V
Z
C
−
−
−
−