Philips S1D13505 用户手册
Epson Research and Development
Page 83
Vancouver Design Center
Hardware Functional Specification
S1D13505
Issue Date: 01/02/02
X23A-A-001-14
Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)
1.
Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2.
t1
min
= t4
min
- 14Ts
3.
t4
min
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
4.
t5
min
= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
5.
t5
min
= [((REG[05h] bits [4:0]) + 1)*8 - 29] Ts
6.
t8
min
= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts
7.
t8
min
= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)
Symbol
Parameter
Min
Typ
Max
Units
t1
FPFRAME setup to FPLINE pulse trailing edge
note 2
t2
FPFRAME hold from FPLINE pulse trailing edge
14
Ts (note 1)
t3
FPLINE pulse width
9
Ts
t4
FPLINE period
note 3
t5a
FPSHIFT2 falling edge to FPLINE pulse leading edge
note 4
t5b
FPSHIFT falling edge to FPLINE pulse leading edge
note 5
t6
FPLINE pulse trailing edge to FPSHIFT2 rising, FPSHIFT falling
edge
edge
t9 + t10
Ts
t7
FPSHIFT2, FPSHIFT period
4
Ts
t8a
FPSHIFT falling edge to FPLINE pulse trailing edge
note 6
t8b
FPSHIFT2 falling edge to FPLINE pulse trailing edge
note 7
t9
FPLINE pulse trailing edge to FPSHIFT rising edge
20
Ts
t10
FPSHIFT2, FPSHIFT pulse width high
2
Ts
t11
FPSHIFT2, FPSHIFT pulse width low
2
Ts
t12
UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
1
Ts
t13
UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1
Ts
FPFRAME
FPLINE
Sync Timing
FPLINE
FPSHIFT
UD[3:0]
LD[3:0]
Data Timing
t9
t1
t2
t4
t3
t6
t7
t11
t10
t12
t13
1
2
t8b
t5b
FPSHIFT2
t8a
t5a