Philips S1D13505 用户手册

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Epson Research and Development

Vancouver Design Center

S1D13505

Hardware Functional Specification

X23A-A-001-14

Issue Date: 01/02/02

7.5.5 8-Bit Single Color Passive LCD Panel Timing (Format 2)

Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2)

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP

= Vertical Non-Display Period

= (REG[0Ah] bits [5:0]) + 1

HDP

= Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= Horizontal Non-Display Period

= ((REG[05h] bits [4:0]) + 1)*8Ts

FPLINE

UD[3:0], LD[3:0]

FPFRAME

FPLINE

MOD

UD2

UD1

UD0

LD3

LD2

LD1

LD0

UD3

MOD

* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel

FPSHIFT

VDP

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

LINE1

LINE2

VNDP

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-R3

1-G3

1-B3

1-R4

1-G4

1-B4

1-R5

1-G5

1-B5

1-R6

1-G6

1-B6

1-R7

1-G7

1-B7

1-R8

1-G8

1-B8

1-G638

1-B638

1-R639

1-G639

1-B639

1-R640

1-G640

1-B640

HDP

HNDP