Cypress CY7C1522AV18 用户手册
CY7C1522AV18, CY7C1529AV18
CY7C1523AV18, CY7C1524AV18
CY7C1523AV18, CY7C1524AV18
Document #: 001-06981 Rev. *D
Page 3 of 30
Logic Block Diagram (CY7C1523AV18)
Logic Block Diagram (CY7C1524AV18)
2
M
x 18 Arra
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read
Add. Decode
Read Data Reg.
LD
Q
[17:0]
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
W
rite Add. D
e
cod
e
Write
Data Reg
Data Reg
18
18
21
18
R/W
LD
R/W
CQ
CQ
DOFF
2
M
x 18 Arra
y
Write
Data Reg
Data Reg
Control
Logic
C
C
18
1M x
18 A
rray
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Re
ad Add. Decode
Read Data Reg.
LD
Q
[35:0]
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
W
rite Add.
Deco
de
Write
Data Reg
Data Reg
36
36
20
36
R/W
LD
R/W
CQ
CQ
DOFF
1M x
18 A
rray
Write
Data Reg
Data Reg
Control
Logic
C
C
36