Cypress STK14C88-5 用户手册
STK14C88-5
Document Number: 001-51038 Rev. **
Page 12 of 17
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
Description
35 ns
45 ns
Unit
Min
Max
Min
Max
t
RC
t
AVAV
STORE/RECALL Initiation Cycle Time
35
45
ns
t
SA
t
AVEL
Address Setup Time
0
0
ns
t
CW
t
ELEH
Clock Pulse Width
25
30
ns
t
HACE
t
ELAX
Address Hold Time
20
20
ns
t
RECALL
RECALL Duration
20
20
μs
Switching Waveforms
Figure 13. CE Controlled Software STORE/RECALL Cycle
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6
#
S
S
E
R
D
D
A
1
#
S
S
E
R
D
D
A
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.