Texas Instruments TMS320DM646x 用户手册
www.ti.com
5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
Ethernet Media Access Controller (EMAC) Registers
The receive unicast clear register (RXUNICASTCLEAR) is shown in
and described in
Figure 63. Receive Unicast Clear Register (RXUNICASTCLEAR)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
RXCH7EN
RXCH6EN
RXCH5EN
RXCH4EN
RXCH3EN
RXCH2EN
RXCH1EN
RXCH0EN
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RXCH7EN
0-1
Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
6
RXCH6EN
0-1
Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
5
RXCH5EN
0-1
Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
4
RXCH4EN
0-1
Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
3
RXCH3EN
0-1
Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
2
RXCH2EN
0-1
Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
1
RXCH1EN
0-1
Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
0
RXCH0EN
0-1
Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
106
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
SPRUEQ6 – December 2007