用户手册目录Table of Contents3Preface101 Introduction121.1 Purpose of the Peripheral121.2 Features121.3 Functional Block Diagram131.4 Industry Standard(s) Compliance Statement142 Architecture142.1 Clock Control142.1.1 MII Clocking142.1.2 GMII Clocking142.2 Memory Map152.3 Signal Descriptions152.3.1 Media Independent Interface (MII) Connections152.3.2 Gigabit Media Independent Interface (GMII) Connections172.4 Ethernet Protocol Overview192.4.1 Ethernet Frame Format192.4.2 Ethernet’s Multiple Access Protocol202.5 Programming Interface202.5.1 Packet Buffer Descriptors202.5.2 Transmit and Receive Descriptor Queues222.5.3 Transmit and Receive EMAC Interrupts232.5.4 Transmit Buffer Descriptor Format242.5.4.1 Next Descriptor Pointer252.5.4.2 Buffer Pointer252.5.4.3 Buffer Offset252.5.4.4 Buffer Length252.5.4.5 Packet Length252.5.4.6 Start of Packet (SOP) Flag252.5.4.7 End of Packet (EOP) Flag262.5.4.8 Ownership (OWNER) Flag262.5.4.9 End of Queue (EOQ) Flag262.5.4.10 Teardown Complete (TDOWNCMPLT) Flag262.5.4.11 Pass CRC (PASSCRC) Flag262.5.5 Receive Buffer Descriptor Format272.5.5.1 Next Descriptor Pointer272.5.5.2 Buffer Pointer272.5.5.3 Buffer Offset282.5.5.4 Buffer Length292.5.5.5 Packet Length292.5.5.6 Start of Packet (SOP) Flag292.5.5.7 End of Packet (EOP) Flag292.5.5.8 Ownership (OWNER) Flag292.5.5.9 End of Queue (EOQ) Flag292.5.5.10 Teardown Complete (TDOWNCMPLT) Flag302.5.5.11 Pass CRC (PASSCRC) Flag302.5.5.12 Jabber Flag302.5.5.13 Oversize Flag302.5.5.14 Fragment Flag302.5.5.15 Undersized Flag302.5.5.16 Control Flag302.5.5.17 Overrun Flag302.5.5.18 Code Error (CODEERROR) Flag302.5.5.19 Alignment Error (ALIGNERROR) Flag302.5.5.20 CRC Error (CRCERROR) Flag302.5.5.21 No Match (NOMATCH) Flag312.6 EMAC Control Module312.6.1 Internal Memory312.6.2 Bus Arbiter312.6.3 Interrupt Control322.6.3.1 Transmit Pulse Interrupt322.6.3.2 Receive Pulse Interrupt322.6.3.3 Receive Threshold Pulse Interrupt332.6.3.4 Miscellaneous Pulse Interrupt332.6.4 Interrupt Pacing332.7 MDIO Module342.7.1 MDIO Module Components342.7.1.1 MDIO Clock Generator342.7.1.2 Global PHY Detection and Link State Monitoring352.7.1.3 Active PHY Monitoring352.7.1.4 PHY Register User Access352.7.2 MDIO Module Operational Overview352.7.2.1 Initializing the MDIO Module362.7.2.2 Writing Data To a PHY Register362.7.2.3 Reading Data From a PHY Register362.7.2.4 Example of MDIO Register Access Code372.8 EMAC Module382.8.1 EMAC Module Components382.8.1.1 Receive DMA Engine382.8.1.2 Receive FIFO382.8.1.3 MAC Receiver392.8.1.4 Receive Address392.8.1.5 Transmit DMA Engine392.8.1.6 Transmit FIFO392.8.1.7 MAC Transmitter392.8.1.8 Statistics Logic392.8.1.9 State RAM392.8.1.10 EMAC Interrupt Controller392.8.1.11 Control Registers and Logic392.8.1.12 Clock and Reset Logic392.8.2 EMAC Module Operational Overview402.9 Media Independent Interface (MII)412.9.1 Data Reception412.9.1.1 Receive Control412.9.1.2 Receive Inter-Frame Interval412.9.1.3 Receive Flow Control412.9.2 Data Transmission432.9.2.1 Transmit Control432.9.2.2 CRC Insertion432.9.2.3 Adaptive Performance Optimization (APO)432.9.2.4 Interpacket-Gap (IPG) Enforcement432.9.2.5 Back Off432.9.2.6 Transmit Flow Control442.9.2.7 Speed, Duplex, and Pause Frame Support442.10 Packet Receive Operation452.10.1 Receive DMA Host Configuration452.10.2 Receive Channel Enabling452.10.3 Receive Address Matching462.10.4 Hardware Receive QOS Support462.10.5 Host Free Buffer Tracking462.10.6 Receive Channel Teardown472.10.7 Receive Frame Classification472.10.8 Promiscuous Receive Mode482.10.9 Receive Overrun492.11 Packet Transmit Operation502.11.1 Transmit DMA Host Configuration502.11.2 Transmit Channel Teardown502.12 Receive and Transmit Latency502.13 Transfer Node Priority512.14 Reset Considerations512.14.1 Software Reset Considerations512.14.2 Hardware Reset Considerations522.15 Initialization522.15.1 Enabling the EMAC/MDIO Peripheral522.15.2 EMAC Control Module Initialization522.15.3 MDIO Module Initialization542.15.4 EMAC Module Initialization552.16 Interrupt Support562.16.1 EMAC Module Interrupt Events and Requests562.16.1.1 Receive Threshold Interrupts562.16.1.2 Transmit Packet Completion Interrupts572.16.1.3 Receive Packet Completion Interrupts572.16.1.4 Statistics Interrupt582.16.1.5 Host Error Interrupt582.16.2 MDIO Module Interrupt Events and Requests592.16.2.1 Link Change Interrupt592.16.2.2 User Access Completion Interrupt592.16.3 Proper Interrupt Processing592.16.4 Interrupt Multiplexing592.17 Power Management602.18 Emulation Considerations603 EMAC Control Module Registers613.1 EMAC Control Module Identification and Version Register (CMIDVER)613.2 EMAC Control Module Software Reset Register (CMSOFTRESET)623.3 EMAC Control Module Emulation Control Register (CMEMCONTROL)623.4 EMAC Control Module Interrupt Control Register (CMINTCTRL)633.5 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)643.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)643.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)653.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)663.9 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)673.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)673.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)683.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT)693.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX)703.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX)704 MDIO Registers714.1 MDIO Version Register (VERSION)714.2 MDIO Control Register (CONTROL)724.3 PHY Acknowledge Status Register (ALIVE)734.4 PHY Link Status Register (LINK)734.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)744.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)754.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)764.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)774.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)784.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)794.11 MDIO User Access Register 0 (USERACCESS0)804.12 MDIO User PHY Select Register 0 (USERPHYSEL0)814.13 MDIO User Access Register 1 (USERACCESS1)824.14 MDIO User PHY Select Register 1 (USERPHYSEL1)835 Ethernet Media Access Controller (EMAC) Registers845.1 Transmit Identification and Version Register (TXIDVER)875.2 Transmit Control Register (TXCONTROL)875.3 Transmit Teardown Register (TXTEARDOWN)885.4 Receive Identification and Version Register (RXIDVER)895.5 Receive Control Register (RXCONTROL)895.6 Receive Teardown Register (RXTEARDOWN)905.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)915.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)925.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)935.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)945.11 MAC Input Vector Register (MACINVECTOR)955.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)955.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)965.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)975.15 Receive Interrupt Mask Set Register (RXINTMASKSET)985.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)995.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)1005.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)1005.19 MAC Interrupt Mask Set Register (MACINTMASKSET)1015.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)1015.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)1025.22 Receive Unicast Enable Set Register (RXUNICASTSET)1055.23 Receive Unicast Clear Register (RXUNICASTCLEAR)1065.24 Receive Maximum Length Register (RXMAXLEN)1075.25 Receive Buffer Offset Register (RXBUFFEROFFSET)1075.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)1085.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)1085.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)1095.29 MAC Control Register (MACCONTROL)1105.30 MAC Status Register (MACSTATUS)1125.31 Emulation Control Register (EMCONTROL)1145.32 FIFO Control Register (FIFOCONTROL)1145.33 MAC Configuration Register (MACCONFIG)1155.34 Soft Reset Register (SOFTRESET)1155.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)1165.36 MAC Source Address High Bytes Register (MACSRCADDRHI)1165.37 MAC Hash Address Register 1 (MACHASH1)1175.38 MAC Hash Address Register 2 (MACHASH2)1175.39 Back Off Test Register (BOFFTEST)1185.40 Transmit Pacing Algorithm Test Register (TPACETEST)1185.41 Receive Pause Timer Register (RXPAUSE)1195.42 Transmit Pause Timer Register (TXPAUSE)1195.43 MAC Address Low Bytes Register (MACADDRLO)1205.44 MAC Address High Bytes Register (MACADDRHI)1215.45 MAC Index Register (MACINDEX)1215.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)1225.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)1225.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)1235.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)1235.50 Network Statistics Registers1245.50.1 Good Receive Frames Register (RXGOODFRAMES)1245.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)1245.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)1245.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)1255.50.5 Receive CRC Errors Register (RXCRCERRORS)1255.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)1255.50.7 Receive Oversized Frames Register (RXOVERSIZED)1255.50.8 Receive Jabber Frames Register (RXJABBER)1265.50.9 Receive Undersized Frames Register (RXUNDERSIZED)1265.50.10 Receive Frame Fragments Register (RXFRAGMENTS)1265.50.11 Filtered Receive Frames Register (RXFILTERED)1265.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)1275.50.13 Receive Octet Frames Register (RXOCTETS)1275.50.14 Good Transmit Frames Register (TXGOODFRAMES)1275.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)1275.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)1285.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)1285.50.18 Deferred Transmit Frames Register (TXDEFERRED)1285.50.19 Transmit Collision Frames Register (TXCOLLISION)1285.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)1285.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)1295.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)1295.50.23 Transmit Late Collision Frames Register (TXLATECOLL)1295.50.24 Transmit Underrun Error Register (TXUNDERRUN)1295.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)1295.50.26 Transmit Octet Frames Register (TXOCTETS)1305.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64)1305.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)1305.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)1305.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)1305.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)1315.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)1315.50.33 Network Octet Frames Register (NETOCTETS)1315.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)1315.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)1325.50.36 Receive DMA Overruns Register (RXDMAOVERRUNS)132Appendix A Glossary133文件大小: 989.9 KB页数: 135Language: English打开用户手册