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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
A simultaneous indication of a stall from both slaves means that a bridge
lock has happened. To resolve this, one of the slaves must back out of its
currently pending transaction. This will allow the other stalled slave to
proceed with its transaction. When the PCI Master detects bridge lock, it
will always signal the PPC Slave to take actions to resolve the bridge lock.
lock has happened. To resolve this, one of the slaves must back out of its
currently pending transaction. This will allow the other stalled slave to
proceed with its transaction. When the PCI Master detects bridge lock, it
will always signal the PPC Slave to take actions to resolve the bridge lock.
If the PPC bus is currently supporting a read cycle of any type, the PPC
Slave will terminate the pending cycle with a retry. Note that if the read
cycle is across a mod-4 address boundary (i.e. from address 0x...02, 3
bytes), it is possible that a portion of the read could have been completed
before the stall condition was detected. The previously read data will be
discarded and the current transaction will be retried.
Slave will terminate the pending cycle with a retry. Note that if the read
cycle is across a mod-4 address boundary (i.e. from address 0x...02, 3
bytes), it is possible that a portion of the read could have been completed
before the stall condition was detected. The previously read data will be
discarded and the current transaction will be retried.
If the PPC bus is currently supporting a posted write transaction, the
transaction will be allowed to complete since this type of transaction is
guaranteed completion. If the PPC bus is currently supporting a non-
posted write transaction, the transaction will be terminated with a retry.
Note that a mod-4 non-posted write transaction could be interrupted
between write cycles, and thereby results in a partially completed write
cycle. It is recommended that write cycles to write-sensitive, non-posted
locations be performed on mod-4 address boundaries.
transaction will be allowed to complete since this type of transaction is
guaranteed completion. If the PPC bus is currently supporting a non-
posted write transaction, the transaction will be terminated with a retry.
Note that a mod-4 non-posted write transaction could be interrupted
between write cycles, and thereby results in a partially completed write
cycle. It is recommended that write cycles to write-sensitive, non-posted
locations be performed on mod-4 address boundaries.
The PCI Master must make the determination to perform the resolution
function since it must make some decisions on possibly removing a
currently pending command from the PPC FIFO.
function since it must make some decisions on possibly removing a
currently pending command from the PPC FIFO.
There are some performance issues related to bridge lock resolution. PHB
offers two mechanism that allow fine tuning of the bridge lock resolution
function.
offers two mechanism that allow fine tuning of the bridge lock resolution
function.
Programmable Lock Resolution
Consider the scenario where the PPC Slave is hosting a read cycle and the
PCI Slave is hosting a posted write transaction. If both transactions happen
at roughly the same time, then the PPC Slave will hold off its transaction
until the PCI Slave can fill the PCI FIFO with write posted data. Once this
happens, both slaves will be stalled and a bridge lock resolution cycle will
happen. The effect of this was to make the PPC Slave waste PPC bus
bandwidth. In addition, a full PCI FIFO will cause the PCI Slave to start
issuing wait states to the PCI bus.
PCI Slave is hosting a posted write transaction. If both transactions happen
at roughly the same time, then the PPC Slave will hold off its transaction
until the PCI Slave can fill the PCI FIFO with write posted data. Once this
happens, both slaves will be stalled and a bridge lock resolution cycle will
happen. The effect of this was to make the PPC Slave waste PPC bus
bandwidth. In addition, a full PCI FIFO will cause the PCI Slave to start
issuing wait states to the PCI bus.