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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
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PCI speculative requesting will only be effective if the PCI arbiter will at
least some times consider the PHB to be a higher priority master than the
master performing the PPC60x bound write cycles. The PCI Master obeys
the PCI specification for benign requests and will unconditionally remove
a speculative request after 16 clocks.
least some times consider the PHB to be a higher priority master than the
master performing the PPC60x bound write cycles. The PCI Master obeys
the PCI specification for benign requests and will unconditionally remove
a speculative request after 16 clocks.
The PHB considers the speculative PCI request mode to be the default
mode of operation. If this is not desired, then the speculative PCI request
mode can be disable by changing the SPRQ bit in the HCSR.
mode of operation. If this is not desired, then the speculative PCI request
mode can be disable by changing the SPRQ bit in the HCSR.
Transaction Ordering
All transactions will be completed on the destination bus in the same order
that they are completed on the originating bus. A read or a compelled write
transaction will force all previously issued write posted transactions to be
flushed from the FIFO. All write posted transfers will be completed before
a read or compelled write begins to ensure that all transfers are completed
in the order issued.
that they are completed on the originating bus. A read or a compelled write
transaction will force all previously issued write posted transactions to be
flushed from the FIFO. All write posted transfers will be completed before
a read or compelled write begins to ensure that all transfers are completed
in the order issued.
All PCI Configuration cycles intended for internal PHB registers will also
be delayed if PHB is busy so that control bits which may affect write
postings do not change until all write posted transactions have completed.
For the same reason all PPC60x write posted transfers will also be
completed before any access to the PHB PPC registers begins.
be delayed if PHB is busy so that control bits which may affect write
postings do not change until all write posted transactions have completed.
For the same reason all PPC60x write posted transfers will also be
completed before any access to the PHB PPC registers begins.
The PCI Local Bus Specification 2.1 states that posted write buffers in both
directions must be flushed before completing a read in either direction.
directions must be flushed before completing a read in either direction.
PHB supports this by providing two optional FIFO flushing options. The
XFBR (PPC60x Flush Before Read) bit within the GCSR register controls
the flushing of PCI write posted data when performing PPC-originated
read transactions. The PFBR (PCI Flush Before Read) bit within the
GCSR register controls the flushing of PPC write posted data when
performing PCI-originated read transactions. The PFBR and XFBR
functions are completely independent of each other; however, both
functions must be enabled to guarantee full compliance with PCI Local
Bus Specification 2.1.
XFBR (PPC60x Flush Before Read) bit within the GCSR register controls
the flushing of PCI write posted data when performing PPC-originated
read transactions. The PFBR (PCI Flush Before Read) bit within the
GCSR register controls the flushing of PPC write posted data when
performing PCI-originated read transactions. The PFBR and XFBR
functions are completely independent of each other; however, both
functions must be enabled to guarantee full compliance with PCI Local
Bus Specification 2.1.
When the XFBR bit is set, the PHB will handle read transactions
originating from the PPC bus in the following manner:
originating from the PPC bus in the following manner: