Motorola MVME5100 用户手册
2-26
Computer Group Literature Center Web Site
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
PCI FIFO
A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between
the PCI Slave and the PPC Master to ensure that optimum data throughput
is maintained. The same FIFO is used for both read and write transactions.
A 52-bit by 4 entry FIFO is used to hold command information being
passed between the PCI Slave and the PPC Master. If write posting is
enabled, then the maximum number of transactions that may be posted is
limited by the abilities of either the data FIFO or the command FIFO. For
example, one burst transaction, 16 double words long, would make the
data FIFO the limiting factor for write posting. Four single beat
transactions would make the command FIFO be the limiting factor. If
either limit is exceeded then any pending PCI transactions are delayed
(TRDY_ is not asserted) until the PPC Master has completed a portion of
the previously posted transactions and created some room within the
command and/or data FIFOs.
the PCI Slave and the PPC Master to ensure that optimum data throughput
is maintained. The same FIFO is used for both read and write transactions.
A 52-bit by 4 entry FIFO is used to hold command information being
passed between the PCI Slave and the PPC Master. If write posting is
enabled, then the maximum number of transactions that may be posted is
limited by the abilities of either the data FIFO or the command FIFO. For
example, one burst transaction, 16 double words long, would make the
data FIFO the limiting factor for write posting. Four single beat
transactions would make the command FIFO be the limiting factor. If
either limit is exceeded then any pending PCI transactions are delayed
(TRDY_ is not asserted) until the PPC Master has completed a portion of
the previously posted transactions and created some room within the
command and/or data FIFOs.
PCI Master
The PCI Master, in conjunction with the capabilities of the PPC Slave,
attempts to move data in either single beat or four-beat (burst) transactions.
The PCI Master supports 32-bit and 64-bit transactions in the following
manner:
attempts to move data in either single beat or four-beat (burst) transactions.
The PCI Master supports 32-bit and 64-bit transactions in the following
manner:
❏
All PPC60x single beat transactions, regardless of the byte count,
are subdivided into one or two 32-bit transfers, depending on the
alignment and the size of the transaction. This includes single beat
8-byte transactions.
are subdivided into one or two 32-bit transfers, depending on the
alignment and the size of the transaction. This includes single beat
8-byte transactions.
❏
All PPC60x burst transactions are transferred in 64-bit mode if the
PCI bus has 64-bit mode enabled. If at any time during the
transaction the PCI target indicates it can not support 64-bit mode,
the PCI Master continues to transfer the remaining data within that
transaction in 32-bit mode.
PCI bus has 64-bit mode enabled. If at any time during the
transaction the PCI target indicates it can not support 64-bit mode,
the PCI Master continues to transfer the remaining data within that
transaction in 32-bit mode.
The PCI Master can support Critical Word First (CWF) burst transfers.
The PCI Master divides this transaction into two parts. The first part starts
on the address presented with the CWF transfer request and continues up
to the end of the current cache line. The second transfer starts at the
beginning of the associated cache line and works its way up to (but not
including) the word addressed by the CWF request.
The PCI Master divides this transaction into two parts. The first part starts
on the address presented with the CWF transfer request and continues up
to the end of the current cache line. The second transfer starts at the
beginning of the associated cache line and works its way up to (but not
including) the word addressed by the CWF request.