Motorola MVME5100 用户手册
Functional Description
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2-27
2
It should be noted that even though the PCI Master can support burst
transactions, a majority of the transaction types handled are single-beat
transfers. Typically PCI space is not configured as cacheable, therefore
burst transactions to PCI space would not naturally occur. It must be
supported since it is conceivable that bursting could happen. For example,
nothing prevents the processor from loading up a cache line with PCI write
data and manually flushing the cache line.
transactions, a majority of the transaction types handled are single-beat
transfers. Typically PCI space is not configured as cacheable, therefore
burst transactions to PCI space would not naturally occur. It must be
supported since it is conceivable that bursting could happen. For example,
nothing prevents the processor from loading up a cache line with PCI write
data and manually flushing the cache line.
The following paragraphs identify some associations between the
operation of the PCI Master and the PCI 2.1 Local Bus Specification
requirements.
operation of the PCI Master and the PCI 2.1 Local Bus Specification
requirements.
Command Types
The PCI Command Codes generated by the PCI Master depend on the type
of transaction being performed on the PPC bus. Please refer to the section
on the PPC Slave earlier in this chapter for a further description of PPC bus
read and PPC bus write. Table 2-8 summarizes the command types
supported and how they are generated.
of transaction being performed on the PPC bus. Please refer to the section
on the PPC Slave earlier in this chapter for a further description of PPC bus
read and PPC bus write. Table 2-8 summarizes the command types
supported and how they are generated.
Table 2-8. PCI Master Command Codes
Entity Addressed
PPC
Transfer Type
Transfer Type
TBST*
MEM
C/BE
PCI Command
PIACK
Read
x
x
0000
Interrupt Acknowledge
CONADD/CONDAT
Write
x
x
0001
Special Cycle
PPC Mapped PCI Space
Read
x
0
0010
I/O Read
Write
x
0
0011
I/O Write
-- Unsupported --
0100
Reserved
-- Unsupported --
0101
Reserved
PPC Mapped PCI Space
Read
1
1
0110
Memory Read
Write
x
1
0111
Memory Write
-- Unsupported --
1000
Reserved
-- Unsupported --
1001
Reserved
CONADD/CONDAT
Read
x
x
1010
Configuration Read
CONADD/CONDAT
Write
x
x
1011
Configuration Write
-- Unsupported --
1100
Memory Read Multiple