Texas Instruments TMS320C645x DSP 用户手册
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4.9
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
MDIO Registers
The MDIO user command complete interrupt (Masked) register (USERINTMASKED) is shown in
and described in
Figure 23. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
31
16
Reserved
R-0
15
2
1
0
Reserved
USERINT
MASKED
R-0
R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 22. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field
Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
USERINTMASKED
Masked value of MDIO User command complete interrupt. When asserted, a bit indicates that
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1. Writing a 1
will clear the interrupt and writing 0 has no effect.
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1. Writing a 1
will clear the interrupt and writing 0 has no effect.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
74
SPRU975B – August 2006