Freescale Semiconductor MCF52210 用户手册
General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
21-7
21.6.4
GPT Output Compare 3 Data Register (GPTOC3D)
NOTE
A successful channel 3 output compare overrides any channel 2:0 compares.
For each OC3M bit that is set, the output compare action reflects the
corresponding OC3D bit.
For each OC3M bit that is set, the output compare action reflects the
corresponding OC3D bit.
21.6.5
GPT Counter Register (GPTCNT)
Table 21-6. GPTOC3M Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
OC3M
Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn
makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare
(IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write
anytime.
1 Corresponding PORTTn pin configured as output
0 No effect
makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare
(IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write
anytime.
1 Corresponding PORTTn pin configured as output
0 No effect
IPSBAR
Offset: 0x1A_0003 (GPTOC3D)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
OC3D
W
Reset:
0
0
0
0
0
0
0
0
Figure 21-5. GPT Output Compare 3 Data Register (GPTOC3D)
Table 21-7. GPTOC3D Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
OC3D
Output compare 3 data. When a successful channel 3 output compare occurs, these bits transfer to the PORTTn
data register if the corresponding OC3Mn bits are set. These bits are read anytime, write anytime.
data register if the corresponding OC3Mn bits are set. These bits are read anytime, write anytime.
IPSBAR
Offset: 0x1A_0004 (GPTCNT)
Access: Supervisor read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CNTR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-6. GPT Counter Register (GPTCNT)