用户手册 — Freescale Semiconductor MCF52210

目录

• Chapter 1 Overview

  17
  • 1.1 MCF52211 Family Configurations

    18
  • 1.2 Block Diagram

    19
  • 1.3 Part Numbers and Packaging

    19
  • 1.2 Features

    20
    • 1.2.1 V2 Core Overview

      24
    • 1.2.2 Integrated Debug Module

      24
    • 1.2.3 JTAG

      25
    • 1.2.4 On-Chip Memories

      26
    • 1.2.5 Power Management

      26
    • 1.2.6 USB On-The-Go Controller

      26
    • 1.2.7 UARTs

      27
    • 1.2.8 I2C Bus

      27
    • 1.2.9 QSPI

      27
    • 1.2.10 Fast ADC

      27
    • 1.2.11 DMA Timers (DTIM0-DTIM3)

      27
    • 1.2.12 General Purpose Timer (GPT)

      28
    • 1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)

      28
    • 1.2.14 Real-Time Clock (RTC)

      28
    • 1.2.15 Pulse-Width Modulation (PWM) Timers

      28
    • 1.2.16 Software Watchdog Timer

      28
    • 1.2.17 Backup Watchdog Timer

      29
    • 1.2.18 Phase-Locked Loop (PLL)

      29
    • 1.2.19 Interrupt Controller (INTC)

      29
    • 1.2.20 DMA Controller

      29
    • 1.2.21 Reset

      29
    • 1.2.22 GPIO

      30
• Chapter 2 Signal Descriptions

  31
  • 2.1 Introduction

    31
  • 2.2 Overview

    31
  • 2.3 Pin Functions

    32
  • 2.4 Reset Signals

    38
  • 2.5 PLL and Clock Signals

    38
  • 2.6 Mode Selection

    38
  • 2.7 External Interrupt Signals

    39
  • 2.8 Queued Serial Peripheral Interface (QSPI)

    39
  • 2.9 I2C I/O Signals

    40
  • 2.10 UART Module Signals

    40
  • 2.11 DMA Timer Signals

    40
  • 2.12 ADC Signals

    41
  • 2.13 General Purpose Timer Signals

    41
  • 2.14 Pulse-Width Modulator Signals

    41
  • 2.15 Debug Support Signals

    41
  • 2.16 EzPort Signal Descriptions

    43
  • 2.17 Power and Ground Pins

    43
• Chapter 3 ColdFire Core

  45
  • 3.1 Introduction

    45
    • 3.1.1 Overview

      45
  • 3.2 Memory Map/Register Description

    46
    • 3.2.1 Data Registers (D0-D7)

      48
    • 3.2.2 Address Registers (A0-A6)

      48
    • 3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

      48
    • 3.2.4 Condition Code Register (CCR)

      49
    • 3.2.5 Program Counter (PC)

      50
    • 3.2.6 Vector Base Register (VBR)

      50
    • 3.2.7 Status Register (SR)

      51
    • 3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR)

      52
  • 3.3 Functional Description

    52
    • 3.3.1 Version 2 ColdFire Microarchitecture

      52
    • 3.3.2 Instruction Set Architecture (ISA_A+)

      57
    • 3.3.3 Exception Processing Overview

      58
    • 3.3.4 Processor Exceptions

      61
    • 3.3.5 Instruction Execution Timing

      69
• Chapter 4 Multiply-Accumulate Unit (MAC)

  77
  • 4.1 Introduction

    77
    • 4.1.1 Overview

      77
  • 4.2 Memory Map/Register Definition

    78
    • 4.2.1 MAC Status Register (MACSR)

      78
    • 4.2.2 Mask Register (MASK)

      80
    • 4.2.3 Accumulator Register (ACC)

      81
  • 4.3 Functional Description

    82
    • 4.3.1 Fractional Operation Mode

      83
    • 4.3.2 MAC Instruction Set Summary

      84
    • 4.3.3 MAC Instruction Execution Times

      85
    • 4.3.4 Data Representation

      85
    • 4.3.5 MAC Opcodes

      85
• Chapter 5 Static RAM (SRAM)

  91
  • 5.1 Introduction

    91
    • 5.1.1 Overview

      91
    • 5.1.2 Features

      91
  • 5.2 Memory Map/Register Description

    91
    • 5.2.1 SRAM Base Address Register (RAMBAR)

      92
  • 5.3 Initialization/Application Information

    93
    • 5.3.1 SRAM Initialization Code

      94
    • 5.3.2 Power Management

      94
• Chapter 6 Clock Module

  95
  • 6.1 Introduction

    95
  • 6.2 Features

    95
  • 6.3 Modes of Operation

    95
    • 6.3.1 Backup Watchdog Timer Mode

      95
    • 6.3.2 RTC Mode

      96
    • 6.3.3 Normal PLL Mode

      96
    • 6.3.4 1:1 PLL Mode

      96
    • 6.3.5 External Clock Mode

      96
  • 6.4 Low-Power Mode Operation

    96
  • 6.5 Block Diagram

    97
  • 6.6 Signal Descriptions

    99
    • 6.6.1 EXTAL

      99
    • 6.6.2 XTAL

      99
    • 6.6.3 CLKOUT

      99
    • 6.6.4 CLKMOD[1:0]

      99
    • 6.6.5 RSTO

      100
  • 6.7 Memory Map and Registers

    100
    • 6.7.1 Register Descriptions

      100
  • 6.8 Functional Description

    111
    • 6.8.1 System Clock Modes

      111
    • 6.8.2 Clock Operation During Reset

      111
    • 6.8.3 System Clock Generation

      112
    • 6.8.4 PLL Operation

      112
• Chapter 7 Backup Watchdog Timer (BWT) Module

  123
  • 7.1 Introduction

    123
    • 7.1.1 Overview

      123
    • 7.1.2 Modes of Operation

      123
  • 7.2 Memory Map and Register Definition

    124
    • 7.2.1 Memory Map

      124
    • 7.2.2 Register Descriptions

      125
  • 7.3 Functional Description

    128
• Chapter 8 Power Management

  129
  • 8.1 Introduction

    129
    • 8.1.1 Features

      129
  • 8.2 Memory Map/Register Definition

    129
    • 8.2.1 Peripheral Power Management Registers (PPMRH, PPMRL)

      130
    • 8.2.2 Low-Power Interrupt Control Register (LPICR)

      133
    • 8.2.3 Peripheral Power Management Set Register (PPMRS)

      135
    • 8.2.4 Peripheral Power Management Clear Register (PPMRC)

      136
    • 8.2.5 Low-Power Control Register (LPCR)

      136
  • 8.3 IPS Bus Timeout Monitor

    137
  • 8.4 Functional Description

    138
    • 8.4.1 Low-Power Modes

      138
    • 8.4.2 Peripheral Behavior in Low-Power Modes

      140
    • 8.4.3 Summary of Peripheral State During Low-Power Modes

      143
• Chapter 9 Chip Configuration Module (CCM)

  145
  • 9.1 Introduction

    145
    • 9.1.1 Features

      145
  • 9.2 External Signal Descriptions

    145
    • 9.2.1 RCON

      146
    • 9.2.2 CLKMOD[1:0]

      146
    • 9.2.3 JTAG_EN

      146
    • 9.2.4 TEST

      146
  • 9.3 Memory Map/Register Definition

    146
    • 9.3.1 Programming Model

      146
    • 9.3.2 Memory Map

      147
    • 9.3.3 Register Descriptions

      147
• Chapter 10 Reset Controller Module

  151
  • 10.1 Introduction

    151
  • 10.2 Features

    151
  • 10.3 Block Diagram

    151
  • 10.4 Signals

    152
    • 10.4.1 RSTI

      152
    • 10.4.2 RSTO

      152
  • 10.5 Memory Map and Registers

    152
    • 10.5.1 Reset Control Register (RCR)

      153
    • 10.5.2 Reset Status Register (RSR)

      154
  • 10.6 Functional Description

    155
    • 10.6.1 Reset Sources

      155
    • 10.6.2 Reset Control Flow

      157
    • 10.6.3 Concurrent Resets

      159
• Chapter 11 Real-Time Clock

  161
  • 11.1 Introduction

    161
    • 11.1.1 Overview

      161
    • 11.1.2 Features

      161
    • 11.1.3 Modes of Operation

      162
  • 11.2 Memory Map/Register Definition

    162
    • 11.2.1 Register Descriptions

      162
  • 11.3 Functional Description

    173
    • 11.3.1 Prescaler and Counter

      173
    • 11.3.2 Alarm

      174
    • 11.3.3 Minute Stopwatch

      174
  • 11.4 Initialization/Application Information

    174
    • 11.4.1 Flow Chart of RTC Operation

      174
    • 11.4.2 Code Example for Initializing the Real-Time Clock

      175
• Chapter 12 System Control Module (SCM)

  177
  • 12.1 Introduction

    177
  • 12.2 Overview

    177
  • 12.3 Features

    177
  • 12.4 Memory Map and Register Definition

    178
  • 12.5 Register Descriptions

    179
    • 12.5.1 Internal Peripheral System Base Address Register (IPSBAR)

      179
    • 12.5.2 Memory Base Address Register (RAMBAR)

      180
    • 12.5.3 Core Reset Status Register (CRSR)

      182
    • 12.5.4 Core Watchdog Control Register (CWCR)

      183
    • 12.5.5 Core Watchdog Service Register (CWSR)

      184
  • 12.6 Internal Bus Arbitration

    185
    • 12.6.1 Overview

      185
    • 12.6.2 Arbitration Algorithms

      186
    • 12.6.3 Bus Master Park Register (MPARK)

      186
  • 12.7 System Access Control Unit (SACU)

    188
    • 12.7.1 Overview

      188
    • 12.7.2 Features

      188
    • 12.7.3 Memory Map/Register Definition

      189
• Chapter 13 General Purpose I/O Module

  195
  • 13.1 Introduction

    195
  • 13.2 Overview

    196
  • 13.3 Features

    196
  • 13.4 Signal Descriptions

    196
  • 13.5 Memory Map/Register Definition

    196
    • 13.5.1 Ports Memory Map

      196
  • 13.6 Register Descriptions

    198
    • 13.6.1 Port Output Data Registers (PORTn)

      198
    • 13.6.2 Port Data Direction Registers (DDRn)

      199
    • 13.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn)

      201
    • 13.6.4 Port Clear Output Data Registers (CLRn)

      203
    • 13.6.5 Pin Assignment Registers

      204
    • 13.6.6 Pad Control Registers

      207
  • 13.7 Ports Interrupts

    209
• Chapter 14 Interrupt Controller Module

  211
  • 14.1 68K/ColdFire Interrupt Architecture Overview

    211
    • 14.1.1 Interrupt Controller Theory of Operation

      212
  • 14.2 Memory Map

    214
  • 14.3 Register Descriptions

    215
    • 14.3.1 Interrupt Pending Registers (IPRHn, IPRLn)

      216
    • 14.3.2 Interrupt Mask Register (IMRHn, IMRLn)

      217
    • 14.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)

      218
    • 14.3.4 Interrupt Request Level Register (IRLRn)

      220
    • 14.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)

      220
    • 14.3.6 Interrupt Control Registers (ICRnx)

      221
    • 14.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn)

      225
    • 14.3.8 Global Level m IACK Registers (GLmIACK)

      226
  • 14.4 Low-Power Wakeup Operation

    226
• Chapter 15 Universal Serial Bus, OTG Capable Controller

  229
  • 15.1 Introduction

    229
    • 15.1.1 USB

      229
    • 15.1.2 USB On-The-Go

      231
    • 15.1.3 USB-FS Features

      232
  • 15.2 Functional Description

    232
    • 15.2.1 Data Structures

      232
  • 15.3 Programmers Interface

    232
    • 15.3.1 Buffer Descriptor Table

      232
    • 15.3.2 Rx vs. Tx as a USB Target Device or USB Host

      233
    • 15.3.3 Addressing Buffer Descriptor Table Entries

      233
    • 15.3.4 Buffer Descriptor Formats

      234
    • 15.3.5 USB Transaction

      236
  • 15.4 Memory Map/Register Definitions

    237
    • 15.4.1 Capability Registers

      238
  • 15.5 OTG and Host Mode Operation

    261
  • 15.6 Host Mode Operation Examples

    262
  • 15.7 On-The-Go Operation

    264
    • 15.7.1 OTG Dual Role A Device Operation

      264
    • 15.7.2 OTG Dual Role B Device Operation

      266
    • 15.7.3 Power

      267
    • 15.7.4 USB Suspend State

      268
• Chapter 16 Edge Port Module (EPORT)

  269
  • 16.1 Introduction

    269
  • 16.2 Low-Power Mode Operation

    270
  • 16.3 Interrupt/GPIO Pin Descriptions

    270
  • 16.4 Memory Map/Register Definition

    270
    • 16.4.1 EPORT Pin Assignment Register (EPPAR)

      271
    • 16.4.2 EPORT Data Direction Register (EPDDR)

      272
    • 16.4.3 Edge Port Interrupt Enable Register (EPIER)

      272
    • 16.4.4 Edge Port Data Register (EPDR)

      273
    • 16.4.5 Edge Port Pin Data Register (EPPDR)

      273
    • 16.4.6 Edge Port Flag Register (EPFR)

      274
• Chapter 17 DMA Controller Module

  275
  • 17.1 Introduction

    275
    • 17.1.1 Overview

      275
    • 17.1.2 Features

      276
  • 17.2 DMA Transfer Overview

    277
  • 17.3 Memory Map/Register Definition

    277
    • 17.3.1 DMA Request Control (DMAREQC)

      278
    • 17.3.2 Source Address Registers (SARn)

      279
    • 17.3.3 Destination Address Registers (DARn)

      279
    • 17.3.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn)

      280
    • 17.3.5 DMA Control Registers (DCRn)

      282
  • 17.4 Functional Description

    285
    • 17.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)

      286
    • 17.4.2 Dual-Address Data Transfer Mode

      286
    • 17.4.3 Channel Initialization and Startup

      287
    • 17.4.4 Data Transfer

      288
    • 17.4.5 Termination

      289
• Chapter 18 ColdFire Flash Module (CFM)

  291
  • 18.1 Introduction

    291
    • 18.1.1 Overview

      291
    • 18.1.2 Features

      292
  • 18.2 External Signal Description

    293
  • 18.3 Memory Map and Register Definition

    293
    • 18.3.1 Memory Map

      293
    • 18.3.2 Flash Base Address Register (FLASHBAR)

      294
    • 18.3.3 Register Descriptions

      297
  • 18.4 Functional Description

    306
    • 18.4.1 General

      306
    • 18.4.2 Flash Normal Mode

      307
    • 18.4.3 Flash Security Operation

      320
• Chapter 19 EzPort

  323
  • 19.1 Features

    323
  • 19.2 Modes of Operation

    323
  • 19.3 External Signal Description

    324
    • 19.3.1 Overview

      324
    • 19.3.2 Detailed Signal Descriptions

      324
  • 19.4 Command Definition

    325
    • 19.4.1 Command Descriptions

      326
  • 19.5 Functional Description

    329
  • 19.6 Initialization/Application Information

    330
• Chapter 20 Programmable Interrupt Timers (PIT0-PIT1)

  331
  • 20.1 Introduction

    331
    • 20.1.1 Overview

      331
    • 20.1.2 Block Diagram

      331
    • 20.1.3 Low-Power Mode Operation

      331
  • 20.2 Memory Map/Register Definition

    332
    • 20.2.1 PIT Control and Status Register (PCSRn)

      333
    • 20.2.2 PIT Modulus Register (PMRn)

      334
    • 20.2.3 PIT Count Register (PCNTRn)

      335
  • 20.3 Functional Description

    335
    • 20.3.1 Set-and-Forget Timer Operation

      335
    • 20.3.2 Free-Running Timer Operation

      336
    • 20.3.3 Timeout Specifications

      336
    • 20.3.4 Interrupt Operation

      336
• Chapter 21 General Purpose Timer Module (GPT)

  339
  • 21.1 Introduction

    339
  • 21.2 Features

    339
  • 21.3 Block Diagram

    340
  • 21.4 Low-Power Mode Operation

    341
  • 21.5 Signal Description

    341
    • 21.5.1 GPT[2:0]

      341
    • 21.5.2 GPT3

      341
    • 21.5.3 SYNCn

      342
  • 21.6 Memory Map and Registers

    342
    • 21.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS)

      343
    • 21.6.2 GPT Compare Force Register (GPCFORC)

      344
    • 21.6.3 GPT Output Compare 3 Mask Register (GPTOC3M)

      344
    • 21.6.4 GPT Output Compare 3 Data Register (GPTOC3D)

      345
    • 21.6.5 GPT Counter Register (GPTCNT)

      345
    • 21.6.6 GPT System Control Register 1 (GPTSCR1)

      346
    • 21.6.7 GPT Toggle-On-Overflow Register (GPTTOV)

      347
    • 21.6.8 GPT Control Register 1 (GPTCTL1)

      347
    • 21.6.9 GPT Control Register 2 (GPTCTL2)

      348
    • 21.6.10 GPT Interrupt Enable Register (GPTIE)

      348
    • 21.6.11 GPT System Control Register 2 (GPTSCR2)

      349
    • 21.6.12 GPT Flag Register 1 (GPTFLG1)

      350
    • 21.6.13 GPT Flag Register 2 (GPTFLG2)

      350
    • 21.6.14 GPT Channel Registers (GPTCn)

      351
    • 21.6.15 Pulse Accumulator Control Register (GPTPACTL)

      351
    • 21.6.16 Pulse Accumulator Flag Register (GPTPAFLG)

      352
    • 21.6.17 Pulse Accumulator Counter Register (GPTPACNT)

      353
    • 21.6.18 GPT Port Data Register (GPTPORT)

      354
    • 21.6.19 GPT Port Data Direction Register (GPTDDR)

      354
  • 21.7 Functional Description

    354
    • 21.7.1 Prescaler

      355
    • 21.7.2 Input Capture

      355
    • 21.7.3 Output Compare

      355
    • 21.7.4 Pulse Accumulator

      356
    • 21.7.5 Event Counter Mode

      356
    • 21.7.6 Gated Time Accumulation Mode

      356
    • 21.7.7 General-Purpose I/O Ports

      357
  • 21.8 Reset

    359
  • 21.9 Interrupts

    359
    • 21.9.1 GPT Channel Interrupts (CnF)

      359
    • 21.9.2 Pulse Accumulator Overflow (PAOVF)

      359
    • 21.9.3 Pulse Accumulator Input (PAIF)

      360
    • 21.9.4 Timer Overflow (TOF)

      360
• Chapter 22 DMA Timers (DTIM0-DTIM3)

  361
  • 22.1 Introduction

    361
    • 22.1.1 Overview

      361
    • 22.1.2 Features

      362
  • 22.2 Memory Map/Register Definition

    362
    • 22.2.1 DMA Timer Mode Registers (DTMRn)

      363
    • 22.2.2 DMA Timer Extended Mode Registers (DTXMRn)

      364
    • 22.2.3 DMA Timer Event Registers (DTERn)

      365
    • 22.2.4 DMA Timer Reference Registers (DTRRn)

      366
    • 22.2.5 DMA Timer Capture Registers (DTCRn)

      367
    • 22.2.6 DMA Timer Counters (DTCNn)

      367
  • 22.3 Functional Description

    368
    • 22.3.1 Prescaler

      368
    • 22.3.2 Capture Mode

      368
    • 22.3.3 Reference Compare

      368
    • 22.3.4 Output Mode

      368
  • 22.4 Initialization/Application Information

    369
    • 22.4.1 Code Example

      369
    • 22.4.2 Calculating Time-Out Values

      370
• Chapter 23 Queued Serial Peripheral Interface (QSPI)

  371
  • 23.1 Introduction

    371
    • 23.1.1 Block Diagram

      371
    • 23.1.2 Overview

      372
    • 23.1.3 Features

      372
    • 23.1.4 Modes of Operation

      372
  • 23.2 External Signal Description

    372
  • 23.3 Memory Map/Register Definition

    373
    • 23.3.1 QSPI Mode Register (QMR)

      373
    • 23.3.2 QSPI Delay Register (QDLYR)

      375
    • 23.3.3 QSPI Wrap Register (QWR)

      376
    • 23.3.4 QSPI Interrupt Register (QIR)

      376
    • 23.3.5 QSPI Address Register (QAR)

      377
    • 23.3.6 QSPI Data Register (QDR)

      378
    • 23.3.7 Command RAM Registers (QCR0-QCR15)

      378
  • 23.4 Functional Description

    379
    • 23.4.1 QSPI RAM

      381
    • 23.4.2 Baud Rate Selection

      382
    • 23.4.3 Transfer Delays

      383
    • 23.4.4 Transfer Length

      384
    • 23.4.5 Data Transfer

      384
  • 23.5 Initialization/Application Information

    385
• Chapter 24 UART Modules

  387
  • 24.1 Introduction

    387
    • 24.1.1 Overview

      387
    • 24.1.2 Features

      388
  • 24.2 External Signal Description

    389
  • 24.3 Memory Map/Register Definition

    389
    • 24.3.1 UART Mode Registers 1 (UMR1n)

      391
    • 24.3.2 UART Mode Register 2 (UMR2n)

      392
    • 24.3.3 UART Status Registers (USRn)

      393
    • 24.3.4 UART Clock Select Registers (UCSRn)

      395
    • 24.3.5 UART Command Registers (UCRn)

      395
    • 24.3.6 UART Receive Buffers (URBn)

      397
    • 24.3.7 UART Transmit Buffers (UTBn)

      398
    • 24.3.8 UART Input Port Change Registers (UIPCRn)

      398
    • 24.3.9 UART Auxiliary Control Register (UACRn)

      399
    • 24.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)

      399
    • 24.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)

      401
    • 24.3.12 UART Input Port Register (UIPn)

      401
    • 24.3.13 UART Output Port Command Registers (UOP1n/UOP0n)

      402
  • 24.4 Functional Description

    402
    • 24.4.1 Transmitter/Receiver Clock Source

      402
    • 24.4.2 Transmitter and Receiver Operating Modes

      404
    • 24.4.3 Looping Modes

      408
    • 24.4.4 Multidrop Mode

      410
    • 24.4.5 Bus Operation

      412
  • 24.5 Initialization/Application Information

    412
    • 24.5.1 Interrupt and DMA Request Initialization

      412
    • 24.5.2 UART Module Initialization Sequence

      414
• Chapter 25 I2C Interface

  421
  • 25.1 Introduction

    421
    • 25.1.1 Block Diagram

      422
    • 25.1.2 Overview

      422
    • 25.1.3 Features

      423
  • 25.2 Memory Map/Register Definition

    423
    • 25.2.1 I2C Address Registers (I2ADRn)

      424
    • 25.2.2 I2C Frequency Divider Registers (I2FDRn)

      424
    • 25.2.3 I2C Control Registers (I2CRn)

      425
    • 25.2.4 I2C Status Registers (I2SRn)

      427
    • 25.2.5 I2C Data I/O Registers (I2DRn)

      428
  • 25.3 Functional Description

    428
    • 25.3.1 START Signal

      428
    • 25.3.2 Slave Address Transmission

      429
    • 25.3.3 Data Transfer

      429
    • 25.3.4 Acknowledge

      430
    • 25.3.5 STOP Signal

      430
    • 25.3.6 Repeated START

      430
    • 25.3.7 Clock Synchronization and Arbitration

      432
    • 25.3.8 Handshaking and Clock Stretching

      433
  • 25.4 Initialization/Application Information

    433
    • 25.4.1 Initialization Sequence

      433
    • 25.4.2 Generation of START

      433
    • 25.4.3 Post-Transfer Software Response

      434
    • 25.4.4 Generation of STOP

      434
    • 25.4.5 Generation of Repeated START

      435
    • 25.4.6 Slave Mode

      435
    • 25.4.7 Arbitration Lost

      435
• Chapter 26 Analog-to-Digital Converter (ADC)

  437
  • 26.1 Introduction

    437
  • 26.2 Features

    437
  • 26.3 Block Diagram

    438
  • 26.4 Memory Map and Register Definition

    438
    • 26.4.1 Control 1 Register (CTRL1)

      439
    • 26.4.2 Control 2 Register (CTRL2)

      441
    • 26.4.3 Zero Crossing Control Register (ADZCC)

      444
    • 26.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2)

      444
    • 26.4.5 Sample Disable Register (ADSDIS)

      446
    • 26.4.6 Status Register (ADSTAT)

      447
    • 26.4.7 Limit Status Register (ADLSTAT)

      449
    • 26.4.8 Zero Crossing Status Register (ADZCSTAT)

      450
    • 26.4.9 Result Registers (ADRSLTn)

      450
    • 26.4.10 Low and High Limit Registers (ADLLMTn and ADHLMTn)

      451
    • 26.4.11 Offset Registers (ADOFSn)

      453
    • 26.4.12 Power Control Register (POWER)

      453
    • 26.4.13 Voltage Reference Register (CAL)

      456
  • 26.5 Functional Description

    457
    • 26.5.1 Input MUX Function

      459
    • 26.5.2 ADC Sample Conversion

      461
    • 26.5.3 ADC Data Processing

      463
    • 26.5.4 Sequential vs. Parallel Sampling

      464
    • 26.5.5 Scan Sequencing

      465
    • 26.5.6 Scan Configuration and Control

      466
    • 26.5.7 Interrupt Sources

      468
    • 26.5.8 Power Management

      468
    • 26.5.9 ADC Clock

      470
    • 26.5.10 Voltage Reference Pins VREFH and VREFL

      473
    • 26.5.11 Supply Pins VDDA and VSSA

      474
• Chapter 27 Pulse-Width Modulation (PWM) Module

  475
  • 27.1 Introduction

    475
    • 27.1.1 Overview

      475
  • 27.2 Memory Map/Register Definition

    476
    • 27.2.1 PWM Enable Register (PWME)

      477
    • 27.2.2 PWM Polarity Register (PWMPOL)

      478
    • 27.2.3 PWM Clock Select Register (PWMCLK)

      478
    • 27.2.4 PWM Prescale Clock Select Register (PWMPRCLK)

      479
    • 27.2.5 PWM Center Align Enable Register (PWMCAE)

      480
    • 27.2.6 PWM Control Register (PWMCTL)

      481
    • 27.2.7 PWM Scale A Register (PWMSCLA)

      482
    • 27.2.8 PWM Scale B Register (PWMSCLB)

      483
    • 27.2.9 PWM Channel Counter Registers (PWMCNTn)

      483
    • 27.2.10 PWM Channel Period Registers (PWMPERn)

      484
    • 27.2.11 PWM Channel Duty Registers (PWMDTYn)

      485
    • 27.2.12 PWM Shutdown Register (PWMSDN)

      486
  • 27.3 Functional Description

    487
    • 27.3.1 PWM Clock Select

      487
    • 27.3.2 PWM Channel Timers

      489
• Chapter 28 Debug Module

  497
  • 28.1 Introduction

    497
    • 28.1.1 Block Diagram

      497
    • 28.1.2 Overview

      497
  • 28.2 Signal Descriptions

    498
  • 28.3 Real-Time Trace Support

    499
    • 28.3.1 Begin Execution of Taken Branch (PST = 0x5)

      501
  • 28.4 Memory Map/Register Definition

    502
    • 28.4.1 Shared Debug Resources

      503
    • 28.4.2 Configuration/Status Register (CSR)

      503
    • 28.4.3 BDM Address Attribute Register (BAAR)

      506
    • 28.4.4 Address Attribute Trigger Register (AATR)

      506
    • 28.4.5 Trigger Definition Register (TDR)

      508
    • 28.4.6 Program Counter Breakpoint/Mask Registers (PBR0-3, PBMR)

      511
    • 28.4.7 Address Breakpoint Registers (ABLR, ABHR)

      513
    • 28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR)

      514
  • 28.5 Background Debug Mode (BDM)

    515
    • 28.5.1 CPU Halt

      515
    • 28.5.2 BDM Serial Interface

      516
    • 28.5.3 BDM Command Set

      518
  • 28.6 Real-Time Debug Support

    535
    • 28.6.1 Theory of Operation

      535
    • 28.6.2 Concurrent BDM and Processor Operation

      537
  • 28.7 Processor Status, Debug Data Definition

    538
    • 28.7.1 User Instruction Set

      538
    • 28.7.2 Supervisor Instruction Set

      543
  • 28.8 Freescale-Recommended BDM Pinout

    543
• Chapter 29 IEEE 1149.1 Test Access Port (JTAG)

  545
  • 29.1 Introduction

    545
    • 29.1.1 Block Diagram

      545
    • 29.1.2 Features

      546
    • 29.1.3 Modes of Operation

      546
  • 29.2 External Signal Description

    546
    • 29.2.1 JTAG Enable (JTAG_EN)

      546
    • 29.2.2 Test Clock Input (TCLK)

      547
    • 29.2.3 Test Mode Select/Breakpoint (TMS/BKPT)

      547
    • 29.2.4 Test Data Input/Development Serial Input (TDI/DSI)

      547
    • 29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK)

      548
    • 29.2.6 Test Data Output/Development Serial Output (TDO/DSO)

      548
  • 29.3 Memory Map/Register Definition

    548
    • 29.3.1 Instruction Shift Register (IR)

      548
    • 29.3.2 IDCODE Register

      548
    • 29.3.3 Bypass Register

      549
    • 29.3.4 JTAG_CFM_CLKDIV Register

      549
    • 29.3.5 TEST_CTRL Register

      549
    • 29.3.6 Boundary Scan Register

      549
  • 29.4 Functional Description

    550
    • 29.4.1 JTAG Module

      550
    • 29.4.2 TAP Controller

      550
    • 29.4.3 JTAG Instructions

      551
  • 29.5 Initialization/Application Information

    554
    • 29.5.1 Restrictions

      554
    • 29.5.2 Nonscan Chain Operation

      554
• Appendix A Register Memory Map Quick Reference

  555
• Appendix B Revision History

  575
  • B.1 Changes between Rev. 1 and Rev. 2

    575
  • B.2 Changes between Rev. 0 and Rev. 1

    576