Freescale Semiconductor MCF52210 用户手册

Freescale Semiconductor

25-3

 

The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of 
operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus 
loading. The maximum communication length and the number of devices connected are limited by a 
maximum bus capacitance of 400 pF.

The I

2

C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data 

corruption in the event that multiple devices attempt to control the bus simultaneously. This feature 
supports complex applications with multiprocessor control and can be used for rapid testing and alignment 
of end products through external connections to an assembly-line computer.

The I

2

C module is compatible with the Philips I

2

C bus protocol. For 

information on system configuration, protocol, and restrictions, see The I

Bus Specification, Version 2.1.

The GPIO module must be configured to enable the peripheral function of 
the appropriate pins (refer to 

) 

prior to configuring the I

2

C module.

The I

2

C module has these key features:

•

Compatibility with I

2

C bus standard version 2.1

•

Support for 3.3-V tolerant devices

•

Multiple-master operation

•

Software-programmable for one of 50 different serial clock frequencies

•

Software-selectable acknowledge bit

•

Interrupt-driven, byte-by-byte data transfer

•

Arbitration-lost interrupt with automatic mode switching from master to slave 

•

Calling address identification interrupt

•

START and STOP signal generation/detection

•

Repeated START signal generation

•

Acknowledge bit generation/detection

•

Bus-busy detection

The below table lists the configuration registers used in the I

2

C interfaces.