Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
201 of 792
NXP Semiconductors
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
6.3 GPIO port output Clear register IOCLR and FIOCLR (IO[0/1]CLR -
0xE002 80[0/1]C and FIO[0/1/2/3/4]CLR - 0x3FFF C0[1/3/5/7/9]C)
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured
as an input or a secondary function, writing to IOCLR has no effect.
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured
as an input or a secondary function, writing to IOCLR has no effect.
Legacy registers are the IO0CLR and IO1CLR while the enhanced GPIOs are supported
via the FIO0CLR, FIO1CLR, FIO2CLR, FIO3CLR, and FIO4CLR registers. Access to a
port pin via the FIOCLR register is conditioned by the corresponding bit of the FIOMASK
register (see
via the FIO0CLR, FIO1CLR, FIO2CLR, FIO3CLR, and FIO4CLR registers. Access to a
port pin via the FIOCLR register is conditioned by the corresponding bit of the FIOMASK
register (see
FIOxSET3
Fast GPIO Port x output Set
register 3. Bit 0 in FIOxSET3
register corresponds to pin
Px.24 ... bit 7 to pin Px.31.
register 3. Bit 0 in FIOxSET3
register corresponds to pin
Px.24 ... bit 7 to pin Px.31.
8 (byte)
R/W
R/W
0x00
FIO0SET3 - 0x3FFF C01B
FIO1SET3 - 0x3FFF C03B
FIO2SET3 - 0x3FFF C05B
FIO3SET3 - 0x3FFF C07B
FIO4SET3 - 0x3FFF C09B
FIO1SET3 - 0x3FFF C03B
FIO2SET3 - 0x3FFF C05B
FIO3SET3 - 0x3FFF C07B
FIO4SET3 - 0x3FFF C09B
FIOxSETL
Fast GPIO Port x output Set
Lower half-word register. Bit 0
in FIOxSETL register
corresponds to pin Px.0 ... bit
15 to pin Px.15.
Lower half-word register. Bit 0
in FIOxSETL register
corresponds to pin Px.0 ... bit
15 to pin Px.15.
16 (half-word)
R/W
R/W
0x0000 FIO0SETL - 0x3FFF C018
FIO1SETL - 0x3FFF C038
FIO2SETL - 0x3FFF C058
FIO3SETL - 0x3FFF C078
FIO4SETL - 0x3FFF C098
FIO2SETL - 0x3FFF C058
FIO3SETL - 0x3FFF C078
FIO4SETL - 0x3FFF C098
FIOxSETU
Fast GPIO Port x output Set
Upper half-word register. Bit 0
in FIOxSETU register
corresponds to Px.16 ... bit
15 to Px.31.
Upper half-word register. Bit 0
in FIOxSETU register
corresponds to Px.16 ... bit
15 to Px.31.
16 (half-word)
R/W
R/W
0x0000 FIO0SETU - 0x3FFF C01A
FIO1SETU - 0x3FFF C03A
FIO2SETU - 0x3FFF C05A
FIO3SETU - 0x3FFF C07A
FIO4SETU - 0x3FFF C09A
FIO2SETU - 0x3FFF C05A
FIO3SETU - 0x3FFF C07A
FIO4SETU - 0x3FFF C09A
Table 166. Fast GPIO port output Set byte and half-word accessible register description
Generic
Register
name
Register
name
Description
Register
length (bits)
& access
length (bits)
& access
Reset
value
value
PORTn Register
Address & Name
Address & Name
Table 167. GPIO port output Clear register (IO0CLR - address 0xE002 800C and IO1CLR -
address 0xE002 801C) bit description
Bit
Symbol
Value Description
Reset
value
value
31:0
P0xCLR
or
P1xCLR
or
P1xCLR
0
Slow GPIO output value Clear bits. Bit 0 in IOxCLR controls pin
Px.0, bit 31 in IOxCLR controls pin Px.31.
Px.0, bit 31 in IOxCLR controls pin Px.31.
Controlled pin output is unchanged.
0x0
1
Controlled pin output is set to LOW.
Table 168. Fast GPIO port output Clear register (FIO[0/1/2/3/4]CLR - address
0x3FFF C0[1/3/5/7/9]C) bit description
Bit
Symbol
Value Description
Reset
value
value
31:0
FP0xCLR
FP1xCLR
FP2xCLR
FP3xCLR
FP4xCLR
FP1xCLR
FP2xCLR
FP3xCLR
FP4xCLR
0
Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin
Px.0, bit 31 controls pin Px.31.
Px.0, bit 31 controls pin Px.31.
Controlled pin output is unchanged.
0x0
1
Controlled pin output is set to LOW.