Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

Writing to the IOPIN register stores the value in the port output register, bypassing the 
need to use both the IOSET and IOCLR registers to obtain the entire written value. This 
feature should be used carefully in an application since it affects the entire port.

Legacy registers are the IO0PIN and IO1PIN while the enhanced GPIOs are supported 
via the FIO0PIN, FIO1PIN, FIO2PIN, FIO3PIN and FIO4PIN registers. Access to a port 
pin via the FIOPIN register is conditioned by the corresponding bit of the  FIOMASK 
register (see 

Only pins masked with zeros in the Mask register (see 

) will be 

correlated to the current content of the Fast GPIO port pin value register.

 

 

Aside from the 32-bit long and word only accessible FIOPIN register, every fast GPIO port 
can also be controlled via several byte and half-word accessible registers listed in 

, too. Next to providing the same functions as the FIOPIN register, these 

additional registers allow easier and faster access to the physical port pins.

31:0

P0xVAL 
or 
P1xVAL

0

Slow GPIO pin value bits. Bit 0 in IOxPIN corresponds to pin 
Px.0, bit 31 in IOxPIN corresponds to pin Px.31.

Controlled pin output is set to LOW.

0x0

1

Controlled pin output is set to HIGH.

31:0

FP0xVAL
FP1xVAL
FP2xVAL
FP3xVAL
FP4xVAL

0

Fast GPIO output value Set bits. Bit 0 in FIOxCLR corresponds 
to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31.

Controlled pin output is set to LOW.

0x0

1

Controlled pin output is set to HIGH.