Nxp Semiconductors UM10237 用户手册

UM10237_2

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continuous memory space; even when a frame is distributed over multiple fragments it will 
typically be in a linear, continuous memory space; when the descriptors wrap at the end of 
the descriptor array the frame will not be in a continuous memory space.

The device driver should enable the receive process by writing a 1 to the RxEnable bit of 
the Command register, after which the MAC needs to be enabled by writing a 1 to the 
‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now 
start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts 
can be disabled by setting the relevant bits in the IntEnable register.

After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In 
this example the number of descriptors is 4. Initially the RxProduceIndex and 
RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex 
== RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex - 
RxProduceIndex - 1 =) 3 descriptors; note the wrapping.

After enabling the receive function in the MAC, data reception will begin starting at the 
next frame i.e. if the receive function is enabled while the (R)MII interface is halfway 
through receiving a frame, the frame will be discarded and reception will start at the next 
frame. The Ethernet block will strip the preamble and start of frame delimiter from the 
frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the 
frame to the first fragment buffer.

Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the 
frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the 
first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA 
will continue filling the second fragment buffer. Since this is a multi-fragment receive, the 
status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the 
RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second 
fragment the Rx DMA will continue writing the third fragment. The status of the second 
fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing 
the three bytes in the third fragment buffer, the end of the frame has been reached and the 
status of the third fragment is written. The third fragment’s status will have the LastFrag bit 
set to 1 and the RxSize equal to 2 (3, -1 encoded).

The next frame received from the (R)MII interface will be written to the fourth fragment 
buffer i.e. five bytes of the third buffer will be unused.

The Rx DMA manager uses an internal tag protocol in the memory interface to check that 
the receive data and status have been committed to memory. After the status of the 
fragments are committed to memory, an RxDoneInt interrupt will be triggered, which 
activates the device driver to inspect the status information. In this example, all 
descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate 
an interrupt after committing data and status to memory.

In this example the receive function cannot read new descriptors as long as the device 
driver does not increment the RxConsumeIndex, because the descriptor array is full (even 
though one descriptor is not programmed yet). Only after the device driver has forwarded 
the receive data to application software, and after the device driver has updated the 
RxConsumeIndex by incrementing it, will the Ethernet block can continue reading 
descriptors and receive data. The device driver will probably increment the 
RxConsumeIndex by 3, since the driver will forward the complete frame consisting of 
three fragments to the application, and hence free up three descriptors at the same time.