Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

The destination address and source address hash CRCs being written in the 
StatusHashCRC word are the nine most significant bits of the 32 bit CRCs as calculated 
by the CRC calculator.

The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex 
mode needs to be configured by the device driver software during initialization.

For a full duplex connection the FullDuplex bit of the Command register needs to be set to 
1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for 
half duplex the same bits need to be set to 0.

For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control 
using pause frames. This type of flow control may be used in full-duplex point-to-point 
connections. Flow control allows a receiver to stall a transmitter e.g. when the receive 
buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the 
transmitting side.

Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles.

In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives 
a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is 
enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the 
RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control 
frames. When a pause frame is received on the Rx side of the Ethernet block, 
transmission on the Tx side will be interrupted after the currently transmitting frame has 
completed, for an amount of time as indicated in the received pause frame. The transmit 
datapath will stop transmitting data for the number of 512 bit slot times encoded in the 
pause-timer field of the received pause control frame.

By default the received pause control frames are not forwarded to the device driver. To 
forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE 
FRAMES’ bit in the MAC1 configuration register.

If case device drivers need to stall the receive data e.g. because software buffers are full, 
the Ethernet block can transmit pause control frames. Transmit flow control needs to be 
initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by 
hardware, such as the DMA managers.

With software flow control, the device driver can detect a situation in which the process of 
receiving frames needs to be interrupted by sending out Tx pause frames. Note that due 
to Ethernet delays, a few frames can still be received before the flow control takes effect 
and the receive stream stops.