Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
347 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is
where N is the number of realized endpoints. Total EP_RAM space should not exceed
4096 bytes (4 kB, 1 kwords).
4096 bytes (4 kB, 1 kwords).
9.5.2 USB Realize Endpoint register (USBReEp - 0xFFE0 C244)
Writing one to a bit in this register causes the corresponding endpoint to be realized.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.
On reset, only the control endpoints are realized. Other endpoints, if required, are realized
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see
.
Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is
shown below.
shown below.
Clear EP_RLZED bit in USBDevIntSt;
for every endpoint to be realized,
{
/* OR with the existing value of the Realize Endpoint register */
TotalEPRAMspace
32
EPRAMspace n
( )
n
0
=
N
∑
+
=
Table 317. USB Realize Endpoint register (USBReEp - address 0xFFE0 C244) bit allocation
Reset value: 0x0000 0003
Bit
31
30
29
28
27
26
25
24
Symbol
EP31
EP30
EP29
EP28
EP27
EP26
EP25
EP24
Bit
23
22
21
20
19
18
17
16
Symbol
EP23
EP22
EP21
EP20
EP19
EP18
EP17
EP16
Bit
15
14
13
12
11
10
9
8
Symbol
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
Bit
7
6
5
4
3
2
1
0
Symbol
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
Table 318. USB Realize Endpoint register (USBReEp - address 0xFFE0 C244) bit description
Bit
Symbol
Value
Description
Reset value
0
EP0
0
Control endpoint EP0 is not realized.
1
1
Control endpoint EP0 is realized.
1
EP1
0
Control endpoint EP1 is not realized.
1
1
Control endpoint EP1 is realized.
31:2
EPxx
0
Endpoint EPxx is not realized.
0
1
Endpoint EPxx is realized.