Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

The DMA engine proceeds with the transfer until the number of bytes specified in the field 
DMA_buffer_length is transferred to or from the USB RAM. Then the EOT interrupt will be 
generated. If this happens in the middle of the packet, the linked DD will get loaded and 
the remaining part of the packet gets transferred to or from the address pointed by the 
new DD.

If the linked DD is not valid and the packet is partially transferred to memory, the DD ends 
with DataOverrun status code set, and the DMA will be disabled for this endpoint. 
Otherwise DD_status will be updated with the NormalCompletion status code.

If the linked DD is not valid and the packet is partially transferred to USB, the DD ends 
with a status code of NormalCompletion in the DD_status field. This situation corresponds 
to the end of the USB transfer, and the packet will be sent as a short packet. Also, when 
the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the 
end of the USB transfer.

The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to 
increase data throughput.

When a double-buffered endpoint is realized, enough space for both endpoint buffers is 
automatically allocated in the EP_RAM.  See 

.

For the following discussion, the endpoint buffer currently accessible to the CPU or DMA 
engine for reading or writing is said to be the active buffer.

For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or 
Validate Buffer commands.

The following example illustrates how double buffering works for a Bulk OUT endpoint in 
Slave mode:

Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is 
B_1. 

1. The host sends a data packet to the endpoint.  The device hardware puts the packet 

into B_1, and generates an endpoint interrupt. 

2. Software clears the endpoint interrupt and begins reading the packet data from B_1.  

While B_1 is still being read, the host sends a second packet, which device hardware 
places in B_2, and generates an endpoint interrupt.

3. Software is still reading from B_1 when the host attempts to send a third packet.  

Since both B_1 and B_2 are full, the device hardware responds with a NAK.

4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer 

command to free B_1 to receive another packet.  B_2 becomes the active buffer.