Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The USB controller is configured using the following registers:

1. Power: In the PCONP register (

), set bit PCUSB.

Remark: On reset, the USB block is disabled (PCUSB = 0).

2. Clock: see 

.

3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to 

PINMODE5 (

4. Wakeup: Use the INTWAKE register (

) to enable activity on the USB bus 

port to wakeup the microcontroller from Power-down mode. 

5. Interrupts: Interrupts are enabled in the VIC using the VICIntEnable register 

).

6. Initialization: see 

.

This section describes the host portion of the USB 2.0 OTG dual role core which 
integrates the host controller (OHCI compliant), device controller and I2C. The I2C 
interface controls the external OTG ATX.

The USB is a 4 wire bus that supports communication between a host and a number (127 
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices 
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic 
configuration of the devices. All transactions are initiated by the host controller. 

The host controller enables data exchange with various USB devices attached to the bus. 
It consists of register interface, serial interface engine and DMA controller. The register 
interface complies to the OHCI specification.

 

OHCI compliant.

AHB

Advanced High-Performance Bus

ATX

Analog Transceiver

DMA

Direct Memory Access

FS

Full Speed

LS

Low Speed

OHCI

Open Host Controller Interface

USB

Universal Serial Bus