Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

[1]

Allowed values for nn are: 10 (high priority) and 01 (low priority).

 

0

scheduler

0

Priority scheduling.

1

1

Uniform (round-robin) scheduling.

2:1

break_burst

00

Break all defined length bursts (the CPU does not create 
defined bursts).

10

01

Break all defined length bursts greater than four-beat.

10

Break all defined length bursts greater than eight-beat.

11

Never break defined length bursts.

3

quantum_type

0

A quantum is an AHB clock.

0

1

A quantum is an AHB bus cycle.

7:4

quantum_size

Controls the type of arbitration and the number of quanta 
before re-arbiration occurs.

0100

0000

Preemptive, re-arbitrate after 1 AHB quantum.

0001

Preemptive, re-arbitrate after 2 AHB quanta.

0010

Preemptive, re-arbitrate after 4 AHB quanta.

0011

Preemptive, re-arbitrate after 8 AHB quanta.

0100

Preemptive, re-arbitrate after 16 AHB quanta.

0101

Preemptive, re-arbitrate after 32 AHB quanta.

0110

Preemptive, re-arbitrate after 64 AHB quanta.

0111

Preemptive, re-arbitrate after 128 AHB quanta.

1000

Preemptive, re-arbitrate after 256 AHB quanta.

1001

Preemptive, re-arbitrate after 512 AHB quanta.

1010

Preemptive, re-arbitrate after 1024 AHB quanta.

1011

Preemptive, re-arbitrate after 2048 AHB quanta.

1100

Preemptive, re-arbitrate after 4096 AHB quanta.

1101

Preemptive, re-arbitrate after 8192 AHB quanta.

1110

Preemptive, re-arbitrate after 16384 AHB quanta.

1111

Non- preemptive, infinite AHB quanta.

9:8

default_master

nn

Master 2 (Ethernet) is the default master.

01

13:12 EP1

nn

External priority for master 1 (CPU).

00

17:16 EP2

nn

External priority for master 2 (Ethernet).

00

31:18 -

-

Reserved. User software should not write ones to 
reserved bits. The value read from a reserved bit is not 
defined.

NA

13:12

EP1

CPU

10 (2)

1

18:16

EP2

Ethernet

01 (1)

2