Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
46 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
•
The IRC oscillator cannot be used as clock source for the USB block.
•
The IRC oscillator cannot be used as clock source for the CAN controllers if the CAN
baud rate is larger than 100 kbit/s.
baud rate is larger than 100 kbit/s.
3.1.1 Clock Source Select register (CLKSRCSEL - 0xE01F C10C)
The PCLKSRCSEL register contains the bits that select the clock source for the PLL.
3.2 PLL (Phase Locked Loop)
The PLL accepts an input clock frequency in the range of 32 kHz to 24 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
3.2.1 PLL operation
The PLL input, in the range of 32 kHZ to 24 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. The multiplier can multiply the input
divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in
the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in
the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
There are additional dividers at the PLL output to bring the frequency down to what is
needed for the CPU, USB, and other peripherals. The PLL output dividers are described
in the Clock Dividers section following the PLL description. A block diagram of the PLL is
shown in
needed for the CPU, USB, and other peripherals. The PLL output dividers are described
in the Clock Dividers section following the PLL description. A block diagram of the PLL is
shown in
Table 42.
Clock Source Select register (CLKSRCSEL - address 0xE01F C10C) bit
description
description
Bit Symbol
Value Description
Reset
value
value
1:0 CLKSRC
Selects the clock source for the PLL as follows:
0
00
Selects the Internal RC oscillator as the PLL clock source
(default).
(default).
01
Selects the main oscillator as the PLL clock source.
10
Selects the RTC oscillator as the PLL clock source.
11
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
Warning: Improper setting of this value, or an incorrect sequence of
changing this value may result in incorrect operation of the device.
changing this value may result in incorrect operation of the device.
7:2 -
0
Unused, always 0.
0