Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

The PLLCON register contains the bits that enable and connect the PLL. Enabling the 
PLL allows it to attempt to lock to the current settings of the multiplier and divider values. 
Connecting the PLL causes the processor and all chip functions to run from the PLL 
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed 
sequence has been given (see 

 

The PLL must be set up, enabled, and Lock established before it may be used as a clock 
source. When switching from the oscillator clock to the PLL output or vice versa, internal 
circuitry synchronizes the operation in order to ensure that glitches are not generated. 
Hardware does not insure that the PLL is locked before it is connected or automatically 

PLLCON

PLL Control Register. Holding register for 
updating PLL control bits. Values written to this 
register do not take effect until a valid PLL feed 
sequence has taken place.

R/W

0

0xE01F C080

PLLCFG

PLL Configuration Register. Holding register for 
updating PLL configuration values. Values 
written to this register do not take effect until a 
valid PLL feed sequence has taken place.

R/W

0

0xE01F C084

PLLSTAT

PLL Status Register. Read-back register for 
PLL control and configuration information. If 
PLLCON or PLLCFG have been written to, but 
a PLL feed sequence has not yet occurred, they 
will not reflect the current PLL state. Reading 
this register provides the actual values 
controlling the PLL, as well as the PLL status.

RO

0

0xE01F C088

PLLFEED

PLL Feed Register. This register enables 
loading of the PLL control and configuration 
information from the PLLCON and PLLCFG 
registers into the shadow registers that actually 
affect PLL operation.

WO

NA

0xE01F C08C

0

PLLE

PLL Enable. When one, and after a valid PLL feed, this bit will 
activate the PLL and allow it to lock to the requested frequency. See 
PLLSTAT register, 

0

1

PLLC

PLL Connect. Having both PLLC and PLLE set to one followed by a 
valid PLL feed sequence, the PLL becomes the clock source for the 
CPU, as well as the USB subsystem and. Otherwise, the clock 
selected by the Clock Source Selection Multiplexer is used directly 
by the LPC2400. See PLLSTAT register, 

.

0

7:2

-

Reserved, user software should not write ones to reserved bits. The 
value read from a reserved bit is not defined.

NA