Nxp Semiconductors UM10237 用户手册

UM10237_2

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When the software is expecting an ”AT" command, it configures the UART1 with the 
expected character format and sets the U1ACR Start bit. The initial values in the divisor 
latches U1DLM and U1DLM don‘t care. Because of the ”A" or ”a" ASCII coding 
(”A" = 0x41, ”a" = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected 
character are delimited by two falling edges. When the U1ACR Start bit is set, the 
auto-baud protocol will execute the following phases:

1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the 

UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.

2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate 

measuring counter will start counting pclk cycles optionally pre-scaled by the 
fractional baud-rate generator.

3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with 

the frequency of the (fractional baud-rate pre-scaled) UART1 input clock, 
guaranteeing the start bit is stored in the U1RSR.

4. During the receipt of the start bit (and the character LSB for mode = 0) the rate 

counter will continue incrementing with the pre-scaled UART1 input clock (pclk).

5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If 

Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.

6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to 

normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt 
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the 
remaining bits of the ”A/a" character.

× CLK

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