Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
462 of 792
NXP Semiconductors
UM10237
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART1 disabled making sure that UART1
is fully software and hardware compatible with UARTs not equipped with this feature.
the register keeps the fractional capabilities of UART1 disabled making sure that UART1
is fully software and hardware compatible with UARTs not equipped with this feature.
UART1 baudrate can be calculated as (n = 1):
(5)
Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud
rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baudrate
generator specific parameters.
rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 0 < MULVAL
≤ 15
2. 0
≤ DIVADDVAL < 15
3. DIVADDVAL<MULVAL
The value of the U1FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
may be lost or corrupted.
If the U1FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
4.16.1 Baudrate calculation
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.
Table 412: UART1 Fractional Divider Register (U1FDR - address 0xE001 0028) bit description
Bit
Function
Value Description
Reset
value
value
3:0
DIVADDVAL
0
Baud-rate generation pre-scaler divisor value. If this field is
0, fractional baud-rate generator will not impact the UARTn
baudrate.
0, fractional baud-rate generator will not impact the UARTn
baudrate.
0
7:4
MULVAL
1
Baud-rate pre-scaler multiplier value. This field must be
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is
used or not.
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is
used or not.
1
31:8
-
NA
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
0
UARTn
baudrate
PCLK
16
256
UnDLM
×
UnDLL
+
(
)
×
1
DivAddVal
MulVal
-----------------------------
+
⎝
⎠
⎛
⎞
×
----------------------------------------------------------------------------------------------------------------------------------
=