Nxp Semiconductors UM10237 用户手册

UM10237_2

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The SSP0/1 interfaces are configured using the following registers:

1. Power: In the PCONP register (

), set bit PCSSP0/1.

Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1).

2. Clock: In PCLK_SEL0 select PCLK_SSP1; in PCLK_SEL1 select PCLK_SSP0 (see 

. In master mode, the clock must be scaled down (see 

).

3. Pins: Select SSP pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to 

). 

4. Interrupts: Interrupts are enabled in the S0SPINT register 

. Interrupts 

are enabled in the VIC using the VICIntEnable register (

Remark: In the VIC, the SSP0 shares its interrupts with the SPI interface.

5. Initialization: see 

 and 

.

Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire 
buses.

Synchronous Serial Communication.

Master or slave operation.

8 frame FIFOs for both transmit and receive.

4 to 16 bits frame.

DMA transfers supported by GPDMA.

The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI, 
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. 
Only a single master and a single slave can communicate on the bus during a given data 
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data 
flowing from the master to the slave and from the slave to the master. In practice it is often 
the case that only one of these data flows carries meaningful data.

LPC2400 has two Synchronous Serial Port controllers -- SSP0 and SSP1.