Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

For device configured as a master in this mode, CLK and FS are forced LOW, and the 
transmit data line DX is tristated whenever the SSP is idle. Once the bottom entry of the 
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be 
transmitted is also transferred from the transmit FIFO to the serial shift register of the 
transmit logic. On the next rising edge of CLK, the MSB of the 4 to 16 bit data frame is 
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR 
pin by the off-chip serial slave device.

Both the SSP and the off-chip serial slave device then clock each data bit into their serial 
shifter on the falling edge of each CLK. The received data is transferred from the serial 
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

The SPI interface is a four-wire interface where the SSEL signal behaves as a slave 
select. The main feature of the SPI format is that the inactive state and phase of the SCK 
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control 
register.

When the CPOL clock polarity control bit is LOW, it produces a steady state low value on 
the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is 
placed on the CLK pin when data is not being transferred.

a. Single frame transfer

b. Continuous/back-to-back frames transfer

CLK

FS

DX/DR

4 to 16 bits

MSB

LSB

CLK

FS

DX/DR

LSB

MSB

LSB

MSB

4 to 16 bits

4 to 16 bits