Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

Note: The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr 
timing constraints.

SEND: The DPSM starts sending data to a card. Depending on the transfer mode bit 
in the data control register, the data transfer mode can be either block or stream:

– In block mode, when the data block counter reaches zero, the DPSM sends an 

internally generated CRC code and end bit, and moves to the BUSY state.

– In stream mode, the DPSM sends data to a card while the enable bit is HIGH and 

the data counter is not zero. It then moves to the IDLE state.

If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the 
IDLE state.

BUSY: The DPSM waits for the CRC status flag:

– If it does not receive a positive CRC status, it moves to the IDLE state and sets the 

CRC fail status flag.

– If it receives a positive CRC status, it moves to the WAIT_S state if MCIDAT0 is not 

LOW (the card is not busy).

If a timeout occurs while the DPSM is in the BUSY state, it sets the data timeout flag and 
moves to the IDLE state.

The data timer is enabled when the DPSM is in the WAIT_R or BUSY state, and 
generates the data timeout error:

When transmitting data, the timeout occurs if the DPSM stays in the BUSY state for 
longer than the programmed timeout period

When receiving data, the timeout occurs if the end of the data is not true, and if the 
DPSM stays in the WAIT_R state for longer than the programmed timeout period.

The data counter has two functions:

To stop a data transfer when it reaches zero. This is the end of the data condition.

To start transferring a pending command (see 

). This is used to send 

the stop command for a stream data transfer.