Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 lists the data path status flags (see 

 for more information).

 

The CRC generator calculates the CRC checksum only for the data bits in a single block, 
and is bypassed in data stream mode. The checksum is a 16 bit value:

    CRC[15:0] = Remainder [(M(x) 

× x

15

) / G(x)]

    G(x) = x

16

 + x

12

 + x

5

 + 1

    M(x) - (first data bit) 

× x

n

 + ... + (last data bit) ¥ X

0

The data FIFO (first-in-first-out) subunit is a data buffer with transmit and receive logic.

The FIFO contains a 32 bit wide, 16-word deep data buffer, and transmit and receive 
logic. Because the data FIFO operates in the APB clock domain (PCLK), all signals from 
the subunits in the MCI clock domain (MCLK) are resynchronized.

Depending on TxActive and RxActive, the FIFO can be disabled, transmit enabled, or 
receive enabled. TxActive and RxActive are driven by the data path subunit and are 
mutually exclusive:

The transmit FIFO refers to the transmit logic and data buffer when TxActive is 
asserted (see 

TxFifoFull

Transmit FIFO is full.

TxFifoEmpty

Transmit FIFO is empty.

TxFifoHalfEmpty

Transmit FIFO is half full.

TxDataAvlbl

Transmit FIFO data available.

TxUnderrun

Transmit FIFO underrun error.

RxFifoFull

Receive FIFO is full.

RxFifoEmpty

Receive FIFO is empty.

RxFifoHalfFull

Receive FIFO is half full.

RxDataAvlbl

Receive FIFO data available.

RxOverrun

Receive FIFO overrun error.

DataBlockEnd

Data block sent/received.

StartBitErr

Start bit not detected on all data signals in wide bus mode.

DataCrcFail

Data packet CRC failed.

DataEnd

Data end (data counter is zero).

DataTimeOut

Data timeout.

TxActive

Data transmission in progress.

RxActive

Data reception in progress.