Nxp Semiconductors UM10237 用户手册

UM10237_2

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When STA is 1 and the I

2

C interface is not already in master mode, it enters master mode, 

checks the bus and generates a START condition if the bus is free. If the bus is not free, it 
waits for a STOP condition (which will free the bus) and generates a START condition 
after a delay of a half clock period of the internal clock generator. If the I

2

C interface is 

already in master mode and data has been transmitted or received, it transmits a repeated 
START condition. STA may be set at any time, including when the I

2

C interface is in an 

addressed slave mode.

STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is 
0, no START condition or repeated START condition will be generated.

If STA and STO are both set, then a STOP condition is transmitted on the I

2

C bus if it the 

interface is in master mode, and transmits a START condition thereafter. If the I

2

C 

interface is in slave mode, an internal STOP condition is generated, but is not transmitted 
on the bus.

STO is the STOP flag. Setting this bit causes the I

2

C interface to transmit a STOP 

condition in master mode, or recover from an error condition in slave mode. When STO is 
1 in master mode, a STOP condition is transmitted on the I

2

C bus. When the bus detects 

the STOP condition, STO is cleared automatically.

In slave mode, setting this bit can recover from an error condition. In this case, no STOP 
condition is transmitted to the bus. The hardware behaves as if a STOP condition has 
been received and it switches to “not addressed” slave receiver mode. The STO flag is 
cleared by hardware automatically.

SI is the I

2

C Interrupt Flag. This bit is set when the I

2

C state changes. However, entering 

state F8 does not set SI since there is nothing for an interrupt service routine to do in that 
case.

While SI is set, the low period of the serial clock on the SCL line is stretched, and the 
serial transfer is suspended. When SCL is high, it is unaffected by the state of the SI flag. 
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register.

AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) 
will be returned during the acknowledge clock pulse on the SCL line on the following 
situations:

1. The address in the Slave Address Register has been received.

2. The general call address has been received while the general call bit (GC) in I2ADR is 

set.

3. A data byte has been received while the I

2

C is in the master receiver mode.

4. A data byte has been received while the I

2

C is in the addressed slave receiver mode.

The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA 
is 0, a not acknowledge (high level to SDA) will be returned during the acknowledge clock 
pulse on the SCL line on the following situations:

1. A data byte has been received while the I

2

C is in the master receiver mode.

2. A data byte has been received while the I

2

C is in the addressed slave receiver mode.