Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
617 of 792
NXP Semiconductors
UM10237
Chapter 23: LPC24XX I
2
S interface
5.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020)
The bit rate for the I
2
S transmitter is determined by the value of the I2STXRATE register.
The value depends on the audio sample rate desired, and the data size and format
(stereo/mono) used. For example, a 48 kHz sample rate for 16 bit stereo data requires a
bit rate of 48,000
(stereo/mono) used. For example, a 48 kHz sample rate for 16 bit stereo data requires a
bit rate of 48,000
×16×2 = 1.536 MHz.
5.10 Receive Clock Rate Register (I2SRXRATE - 0xE008 8024)
The bit rate for the I
2
S receiver is determined by the value of the I2SRXRATE register.
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for I2STXRATE.
The calculation is the same as for I2STXRATE.
6.
I
2
S transmit and receive interfaces
The I
2
S interface can transmit and receive 8, 16 or 32 bits stereo or mono audio
information. Some details of I
2
S implementation are:
•
When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.
until new data is written to the FIFO.
•
When mute is true, the data value 0 is transmitted.
•
When mono is false, two successive data words are respectively left and right data.
Table 539: Interrupt Request Control register (I2SIRQ - address 0xE008 801C) bit description
Bit
Symbol
Description
Reset
Value
Value
0
rx_Irq_enable
When 1, enables I2S receive interrupt.
0
1
tx_Irq_enable
When 1, enables I2S transmit interrupt.
0
7:2
Unused
Unused.
0
15:8
rx_depth_Irq
Set the FIFO level on which to create an irq request.
0
23:16
tx_depth_Irq
Set the FIFO level on which to create an irq request.
0
31:24
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 540: Transmit Clock Rate register (I2TXRATE - address 0xE008 8020) bit description
Bit
Symbol
Description
Reset
Value
Value
9:0
tx_rate
I
2
S transmit bit rate. This value plus one is used to divide PCLK by
to produce the transmit bit clock. Ten bits of divide supports a wide
range of I
range of I
2
S rates over a wide range of pclk rates.
0
15:10
Unused
Unused.
0
Table 541: Receive Clock Rate register (I2SRXRATE - address 0xE008 8024) bit description
Bit
Symbol
Description
Reset
Value
Value
9:0
rx_rate
I
2
S receive bit rate. This value plus one is used to divide PCLK by
to produce the receive bit clock. Ten bits of divide supports a wide
range of I
range of I
2
S rates over a wide range of pclk rates.
0
15:10
Unused
Unused.
0