Nxp Semiconductors UM10237 用户手册

UM10237_2

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Data word length is determined by the wordwidth value in the configuration register. 
There is a separate wordwidth value for the receive channel and the transmit channel.

– 0: word is considered to contain four 8 bits data words.

– 1: word is considered to contain two 16 bits data words.

– 3: word is considered to contain one 32 bits data word.

When the transmit FIFO contains insufficient data the transmit channel will repeat 
transmitting the last data until new data is available. This can occur when the 
microprocessor or the DMA at some time is unable to provide new data fast enough. 
Because of this delay in new data there is a need to fill the gap, which is 
accomplished by continuing to transmit the last sample. The data is not muted as this 
would produce an noticeable and undesirable effect in the sound.

The transmit channel and the receive channel only handle 32 bit aligned words, data 
chunks must be clipped or extended to a multiple of 32 bits.

When switching between data width or modes the I2S must be reset via the reset bit in the 
control register in order to ensure correct synchronization. It is advisable to set the stop bit 
also until sufficient data has been written in the transmit FIFO. Note that when stopped 
data output is muted.

All data accesses to FIFO's are 32 bits. 

 shows the possible data 

sequences.

A data sample in the FIFO consists of:

1

×32 bits in 8 or 16 bit stereo modes.

1

×32 bits in mono modes.

2

×32 bits, first left data, second right data, in 32 bit stereo modes.

Data is read from the transmit FIFO after the falling edge of WS, it will be transferred to 
the transmit clock domain after the rising edge of WS. On the next falling edge of WS the 
left data will be loaded in the shift register and transmitted and on the following rising edge 
of WS the right data is loaded and transmitted.

The receive channel will start receiving data after a change of WS. When word select 
becomes low it expects this data to be left data, when WS is high received data is 
expected to be right data. Reception will stop when the bit counter has reached the limit 
set by wordwidth. On the next change of WS the received data will be stored in the 
appropriate hold register. When complete data is available it will be written into the receive 
FIFO.

Handling of data for transmission and reception is performed via the FIFO controller which 
can generate two DMA requests and an interrupt request. The controller consists of a set 
of comparators which compare FIFO levels with depth settings contained in registers. The 
current status of the level comparators can be seen in the APB status register.