Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
625 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
6.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR
register, the Timer Counter register will be incremented.
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR
register, the Timer Counter register will be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Table 548: Timer Control Register (TCR, TIMERn: TnTCR - addresses 0xE000 4004,
0xE000 8004, 0xE007 0004, 0xE007 4004) bit description
Bit
Symbol
Description
Reset Value
0
Counter Enable When one, the Timer Counter and Prescale Counter are
enabled for counting. When zero, the counters are
disabled.
disabled.
0
1
Counter Reset
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
0
7:2
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 549: Count Control Register (T[0/1/2/3]CTCR - addresses 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070) bit description
Bit
Symbol
Value
Description
Reset
Value
Value
1:0
Counter/
Timer
Mode
Timer
Mode
00
This field selects which rising PCLK edges can increment
Timer’s Prescale Counter (PC), or clear PC and increment
Timer Counter (TC).
Timer’s Prescale Counter (PC), or clear PC and increment
Timer Counter (TC).
Timer Mode: the TC is incremented when the Prescale
Counter matches the Prescale Register.
Counter matches the Prescale Register.
Timer Mode: every rising PCLK edge
00
01
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
CAP input selected by bits 3:2.
10
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
CAP input selected by bits 3:2.
11
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
input selected by bits 3:2.