Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
627 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Table 550: Match Control Register (T[0/1/2/3]MCR - addresses 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014) bit description
Bit
Symbol Value Description
Reset
Value
Value
0
MR0I
1
Interrupt on MR0: an interrupt is generated when MR0 matches
the value in the TC.
the value in the TC.
0
0
This interrupt is disabled
1
MR0R
1
Reset on MR0: the TC will be reset if MR0 matches it.
0
0
Feature disabled.
2
MR0S
1
Stop on MR0: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR0 matches the TC.
set to 0 if MR0 matches the TC.
0
0
Feature disabled.
3
MR1I
1
Interrupt on MR1: an interrupt is generated when MR1 matches
the value in the TC.
the value in the TC.
0
0
This interrupt is disabled
4
MR1R
1
Reset on MR1: the TC will be reset if MR1 matches it.
0
0
Feature disabled.
5
MR1S
1
Stop on MR1: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR1 matches the TC.
set to 0 if MR1 matches the TC.
0
0
Feature disabled.
6
MR2I
1
Interrupt on MR2: an interrupt is generated when MR2 matches
the value in the TC.
the value in the TC.
0
0
This interrupt is disabled
7
MR2R
1
Reset on MR2: the TC will be reset if MR2 matches it.
0
0
Feature disabled.
8
MR2S
1
Stop on MR2: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR2 matches the TC.
set to 0 if MR2 matches the TC.
0
0
Feature disabled.
9
MR3I
1
Interrupt on MR3: an interrupt is generated when MR3 matches
the value in the TC.
the value in the TC.
0
0
This interrupt is disabled
10
MR3R
1
Reset on MR3: the TC will be reset if MR3 matches it.
0
0
Feature disabled.
11
MR3S
1
Stop on MR3: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR3 matches the TC.
set to 0 if MR3 matches the TC.
0
0
Feature disabled.
15:12 -
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA