Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

[1]

Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset. These 
registers must be initialized by software if the RTC is enabled. Reset Value reflects the data stored in used 
bits only. It does not include reserved bits content.

Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter 
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register 
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR 
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the 
time counters. If CIIR is enabled for a particular counter, then every time the counter is 
incremented an interrupt is generated. The alarm registers allow the user to specify a date 
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm 
compares. If all nonmasked alarm registers match the value in their corresponding time 
counter, then an interrupt is generated.

The RTC interrupt can bring the microcontroller out of power-down mode if the RTC is 
operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is enabled 
for wakeup and its selected event occurs, the oscillator wakeup cycle associated with the 
XTAL1/2 pins is started. For details on the RTC based wakeup process see 

 and 

 summarizes the registers located from 0 to 7 of A[6:2]. More detailed 

descriptions follow.

 

The Interrupt Location Register is a 2 bit register that specifies which blocks are 
generating an interrupt (see 

). Writing a one to the appropriate bit clears the 

corresponding interrupt. Writing a zero has no effect. This allows the programmer to read 
this register and write back the same value to clear only the interrupt that is detected by 
the read.

ILR

3

Interrupt Location. Reading this location indicates 
the source of an interrupt. Writing a one to the 
appropriate bit at this location clears the associated 
interrupt.

R/W

0xE002 4000

CTC

15

Clock Tick Counter. Value from the clock divider.

RO

0xE002 4004

CCR

4

Clock Control Register. Controls the function of the 
clock divider.

R/W

0xE002 4008

CIIR

8

Counter Increment Interrupt. Selects which counters 
will generate an interrupt when they are 
incremented.

R/W

0xE002 400C

AMR

8

Alarm Mask Register. Controls which of the alarm 
registers are masked.

R/W

0xE002 4010

CTIME0

32

Consolidated Time Register 0

RO

0xE002 4014

CTIME1

32

Consolidated Time Register 1

RO

0xE002 4018

CTIME2

32

Consolidated Time Register 2

RO

0xE002 401C