Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
652 of 792
NXP Semiconductors
UM10237
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
6.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
one to bit zero of the Interrupt Location Register (ILR[0]).
every time a counter is incremented. This interrupt remains valid until cleared by writing a
one to bit zero of the Interrupt Location Register (ILR[0]).
6.2.5 Counter Increment Select Mask Register (CISS - 0xE002 4040)
The CISS register provides a way to obtain millisecond-range periodic CPU interrupts
from the Real Time Clock. This can allow freeing up one of the general purpose timers, or
support power saving by putting the CPU into a reduced power mode between periodic
interrupts.
from the Real Time Clock. This can allow freeing up one of the general purpose timers, or
support power saving by putting the CPU into a reduced power mode between periodic
interrupts.
Carry out signals from different stages of the Clock Tick Counter are used to generate the
sub-second interrupts. The possibilities range from 16 counts of the CTC (about
488 microseconds), up to 2,048 counts of the CTC (about 62.5 milliseconds). The
available counts and corresponding times are given in
sub-second interrupts. The possibilities range from 16 counts of the CTC (about
488 microseconds), up to 2,048 counts of the CTC (about 62.5 milliseconds). The
available counts and corresponding times are given in
3:2
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
4
CLKSRC
If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler,
as on earlier devices in the NXP Embedded ARM family. If this bit is 1,
the CTC takes its clock from the 32 kHz oscillator that’s connected to
the RTCX1 and RTCX2 pins (see
as on earlier devices in the NXP Embedded ARM family. If this bit is 1,
the CTC takes its clock from the 32 kHz oscillator that’s connected to
the RTCX1 and RTCX2 pins (see
for hardware details).
NA
7:5
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
Table 570. Clock Control Register (CCR - address 0xE002 4008) bit description
Bit
Symbol
Description
Reset
value
value
Table 571. Counter Increment Interrupt Register (CIIR - address 0xE002 400C) bit description
Bit
Symbol
Description
Reset
value
value
0
IMSEC
When 1, an increment of the Second value generates an interrupt.
NA
1
IMMIN
When 1, an increment of the Minute value generates an interrupt.
NA
2
IMHOUR
When 1, an increment of the Hour value generates an interrupt.
NA
3
IMDOM
When 1, an increment of the Day of Month value generates an
interrupt.
interrupt.
NA
4
IMDOW
When 1, an increment of the Day of Week value generates an interrupt. NA
5
IMDOY
When 1, an increment of the Day of Year value generates an interrupt.
NA
6
IMMON
When 1, an increment of the Month value generates an interrupt.
NA
7
IMYEAR
When 1, an increment of the Year value generates an interrupt.
NA