Nxp Semiconductors UM10237 用户手册

UM10237_2

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during system operation (by reconfiguring the PLL, the APB divider, or the RTC prescaler) 
will result in some form of accumulated time error. Accumulated time errors may occur in 
case RTC clock source is switched between the PCLK to the RTCX pins, too.

Once the 32 kHz signal from RTCX1-2 pins is selected as a clock source, the RTC can 
operate completely without the presence of the APB clock (PCLK). Therefore, power 
sensitive applications (i.e. battery powered application) utilizing the RTC will reduce the 
power consumption by using the signal from RTCX1-2 pins, and writing a 0 into the 
PCRTC bit in the PCONP power control register (see 

Remark: Note that if the RTC is running from the 32 kHz signal and powered by VBAT, the 
internal registers can be read. However, they cannot be written to unless the PCRTC bit in 
the PCONP register is set to 1, see 

The RTC may be clocked by either the 32.786 kHz RTC oscillator, or by the APB 
peripheral clock (PCLK) after adjustment by the reference clock divider.

The reference clock divider (hereafter referred to as the Prescaler) may be used when the 
RTC clock source is not supplied by the RTC oscillator, but comes from the APB 
peripheral clock (PCLK).

The Prescaler allows generation of a 32.768 kHz reference clock from any PCLK 
frequency greater than or equal to 65.536 kHz (2

× 32.768 kHz). This permits the RTC to 

always run at the proper rate regardless of the peripheral clock rate. Basically, the 
Prescaler divides PCLK by a value which contains both an integer portion and a fractional 
portion. The result is not a continuous output at a constant frequency, some clock periods 
will be one PCLK longer than others. However, the overall result can always be 32,768 
counts per second.

The reference clock divider consists of a 13 bit integer counter and a 15 bit fractional 
counter. The reasons for these counter sizes are as follows:

1. For frequencies that are expected to be supported by the LPC2400, a 13 bit integer 

counter is required. This can be calculated as 160 MHz divided by 32,768 minus 1 
equals 4881 with a remainder of 26,624. Thirteen bits are needed to hold the value 
4881, but actually supports frequencies up to 268.4 MHz (32,768

× 8192).

2. The remainder value could be as large as 32,767, which requires 15 bits.

 

This is the integer portion of the prescale value, calculated as:

PREINT

13

Prescale Value, integer portion

R/W

0xE002 4080

PREFRAC 15

Prescale Value, fractional portion

R/W

0xE002 4084