Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The Prescaler block labelled "Combination Logic" in 

 determines when the 

decrement of the 13 bit PREINT counter is extended by one PCLK. In order to both insert 
the correct number of longer cycles, and to distribute them evenly, the combinatorial Logic 
associates each bit in PREFRAC with a combination in the 15 bit Fraction Counter. These 
associations are shown in the following 

.

For example, if PREFRAC bit 14 is a one (representing the fraction 1/2), then half of the 
cycles counted by the 13 bit counter need to be longer. When there is a 1 in the LSB of the 
Fraction Counter, the logic causes every alternate count (whenever the LSB of the 
Fraction Counter=1) to be extended by one PCLK, evenly distributing the pulse widths. 
Similarly, a one in PREFRAC bit 13 (representing the fraction 1/4) will cause every fourth 
cycle (whenever the two LSBs of the Fraction Counter = 10) counted by the 13 bit counter 
to be longer.

to clock tick counter

13 BIT INTEGER COUNTER

(DOWN COUNTER)

15 BIT FRACTION COUNTER

COMBINATORIAL LOGIC

15 BIT FRACTION REGISTER

(PREFRAC)

15

15

15

13 BIT RELOAD INTEGER

REGISTER

(PREINT)

13

13

APB bus

PCLK

(APB clock)

CLK

CLK

RELOAD

UNDERFLOW

extend

reload