Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
668 of 792
NXP Semiconductors
UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
Remark: When the ADC is not used, the V
DDA
and VREF pins must be connected to the
power supply, and pin V
SSA
must be grounded. These pins should not be left floating.
5.
Register description
The base address of the ADC is 0xE003 4000. The A/D Converter includes registers as
shown in
shown in
Table 592. ADC pin description
Pin
Type
Description
AD0[7:0]
Input
Analog Inputs.
The A/D converter cell can measure the voltage on any of these input signals.
Note that these analog inputs are always connected to their pins, even if the Pin Multiplexing
Register assigns them to port pins. A simple self-test of the A/D Converter can be done by driving
these pins as port outputs.
Register assigns them to port pins. A simple self-test of the A/D Converter can be done by driving
these pins as port outputs.
Note:
while the ADC pins are specified as 5 V tolerant (see
), the analog multiplexing
in the ADC block is not. More than V
DD(3V3)
/VREF/3.3 V (V
DDA
) should not be applied to any pin
that is selected as an ADC input, or the ADC reading will be incorrect. If for example AD0.0 and
AD0.1 are used as the ADC0 inputs and voltage on AD0.0 = 4.5 V while AD0.1 = 2.5 V, an
excessive voltage on the AD0.0 can cause an incorrect reading of the AD0.1, although the AD0.1
input voltage is within the right range.
AD0.1 are used as the ADC0 inputs and voltage on AD0.0 = 4.5 V while AD0.1 = 2.5 V, an
excessive voltage on the AD0.0 can cause an incorrect reading of the AD0.1, although the AD0.1
input voltage is within the right range.
If the A/D converter is not used in an application then the pins associated with A/D inputs can be
used as 5V tolerant digital IO pins
used as 5V tolerant digital IO pins
VREF
Reference Voltage Reference. This pin provides a voltage reference level for the A/D converter.
V
DDA
, V
SSA
Power
Analog Power and Ground.
These should be nominally the same voltages as V
DD(3V3)
and V
SS
respectively but should be isolated to minimize noise and error.
Table 593. Summary of ADC registers
Name
Description
Access Reset
Value
Address
AD0CR
A/D Control Register. The AD0CR register
must be written to select the operating mode
before A/D conversion can occur.
must be written to select the operating mode
before A/D conversion can occur.
R/W
0x0000 0001 0xE003 4000
AD0GDR
A/D Global Data Register. Contains the result
of the most recent A/D conversion.
of the most recent A/D conversion.
R/W
NA
0xE003 4004
AD0STAT
A/D Status Register. This register contains
DONE and OVERRUN flags for all of the A/D
channels, as well as the A/D interrupt flag.
DONE and OVERRUN flags for all of the A/D
channels, as well as the A/D interrupt flag.
RO
0
0xE003 4030
AD0INTEN A/D Interrupt Enable Register. This register
contains enable bits that allow the DONE flag
of each A/D channel to be included or
excluded from contributing to the generation
of an A/D interrupt.
of each A/D channel to be included or
excluded from contributing to the generation
of an A/D interrupt.
R/W
0x0000 0100 0xE003 400C
AD0DR0
A/D Channel 0 Data Register. This register
contains the result of the most recent
conversion completed on channel 0
contains the result of the most recent
conversion completed on channel 0
R/W
NA
0xE003 4010
AD0DR1
A/D Channel 1 Data Register. This register
contains the result of the most recent
conversion completed on channel 1.
contains the result of the most recent
conversion completed on channel 1.
R/W
NA
0xE003 4014
AD0DR2
A/D Channel 2 Data Register. This register
contains the result of the most recent
conversion completed on channel 2.
contains the result of the most recent
conversion completed on channel 2.
R/W
NA
0xE003 4018